class TargetSubtargetInfo

Declaration

class TargetSubtargetInfo : public MCSubtargetInfo { /* full declaration omitted */ };

Description

TargetSubtargetInfo - Generic base class for all target subtargets. All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:62

Inherits from: MCSubtargetInfo

Method Overview

Inherited from MCSubtargetInfo:

Methods

TargetSubtargetInfo()

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:78

TargetSubtargetInfo(
    const llvm::TargetSubtargetInfo&)

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:79

Parameters

const llvm::TargetSubtargetInfo& 

TargetSubtargetInfo(
    const llvm::Triple& TT,
    llvm::StringRef CPU,
    llvm::StringRef FS,
    ArrayRef<llvm::SubtargetFeatureKV> PF,
    ArrayRef<llvm::SubtargetSubTypeKV> PD,
    const llvm::MCWriteProcResEntry* WPR,
    const llvm::MCWriteLatencyEntry* WL,
    const llvm::MCReadAdvanceEntry* RA,
    const llvm::InstrStage* IS,
    const unsigned int* OC,
    const unsigned int* FP)

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:64

Parameters

const llvm::Triple& TT
llvm::StringRef CPU
llvm::StringRef FS
ArrayRef<llvm::SubtargetFeatureKV> PF
ArrayRef<llvm::SubtargetSubTypeKV> PD
const llvm::MCWriteProcResEntry* WPR
const llvm::MCWriteLatencyEntry* WL
const llvm::MCReadAdvanceEntry* RA
const llvm::InstrStage* IS
const unsigned int* OC
const unsigned int* FP

virtual bool addrSinkUsingGEPs() const

Description

Sink addresses into blocks using GEP instructions rather than pointer casts and arithmetic.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:281

virtual void adjustSchedDependency(
    llvm::SUnit* def,
    llvm::SUnit* use,
    llvm::SDep& dep) const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:229

Parameters

llvm::SUnit* def
llvm::SUnit* use
llvm::SDep& dep

virtual bool enableAdvancedRASplitCost() const

Description

True if the subtarget should consider the cost of local intervals created by a split candidate when choosing the best split candidate. This heuristic may be compile time intensive.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:273

virtual bool enableAtomicExpand() const

Description

True if the subtarget should run the atomic expansion pass.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:214

virtual bool enableEarlyIfConversion() const

Description

Enable the use of the early if conversion pass.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:286

virtual bool enableIndirectBrExpand() const

Description

True if the subtarget should run the indirectbr expansion pass.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:217

virtual bool enableJoinGlobalCopies() const

Description

True if the subtarget should enable joining global copies. By default this is enabled if the machine scheduler is enabled, but can be overridden.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:201

virtual bool enableMachinePipeliner() const

Description

True if the subtarget should run MachinePipeliner

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:195

virtual bool enableMachineSchedDefaultSched()
    const

Description

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:192

virtual bool enableMachineScheduler() const

Description

True if the subtarget should run MachineScheduler after aggressive coalescing. This currently replaces the SelectionDAG scheduler with the "source" order scheduler (though see below for an option to turn this off and use the TargetLowering preference). It does not yet disable the postRA scheduler.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:188

virtual bool enablePostRAMachineScheduler() const

Description

True if the subtarget should run a machine scheduler after register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:211

virtual bool enablePostRAScheduler() const

Description

True if the subtarget should run a scheduler after register allocation. By default this queries the PostRAScheduling bit in the scheduling model which is the preferred way to influence this.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:207

virtual bool enableRALocalReassignment(
    CodeGenOpt::Level OptLevel) const

Description

True if the subtarget should run the local reassignment heuristic of the register allocator. This heuristic may be compile time intensive, \p OptLevel provides a finer grain to tune the register allocator.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:268

Parameters

CodeGenOpt::Level OptLevel

virtual bool enableSubRegLiveness() const

Description

Enable tracking of subregister liveness in register allocator. Please use MachineRegisterInfo::subRegLivenessEnabled() instead where possible.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:298

virtual llvm::TargetSubtargetInfo::
    AntiDepBreakMode
    getAntiDepBreakMode() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:233

virtual const llvm::CallLowering*
getCallLowering() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:103

virtual void getCriticalPathRCs(
    llvm::TargetSubtargetInfo::RegClassVector&
        CriticalPathRCs) const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:238

Parameters

llvm::TargetSubtargetInfo::RegClassVector& CriticalPathRCs

virtual std::unique_ptr<PBQPRAConstraint>
getCustomPBQPConstraints() const

Description

Return PBQPConstraint(s) for the target. Override to provide custom PBQP constraints.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:291

virtual RegisterScheduler::FunctionPassCtor
getDAGScheduler(CodeGenOpt::Level) const

Description

Target can subclass this hook to select a different DAG scheduler.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:115

Parameters

CodeGenOpt::Level 

virtual const llvm::TargetFrameLowering*
getFrameLowering() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:96

virtual const llvm::TargetInstrInfo*
getInstrInfo() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:95

virtual const llvm::InstrItineraryData*
getInstrItineraryData() const

Description

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:131

virtual llvm::InstructionSelector*
getInstructionSelector() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:109

virtual const llvm::LegalizerInfo*
getLegalizerInfo() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:119

virtual CodeGenOpt::Level
getOptLevelToEnablePostRAScheduler() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:260

virtual void getPostRAMutations(
    std::vector<
        std::unique_ptr<ScheduleDAGMutation>>&
        Mutations) const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:244

Parameters

std::vector<std::unique_ptr<ScheduleDAGMutation>>& Mutations

virtual const llvm::RegisterBankInfo*
getRegBankInfo() const

Description

If the information for the register banks is available, return it. Otherwise return nullptr.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:127

virtual const llvm::TargetRegisterInfo*
getRegisterInfo() const

Description

getRegisterInfo - If register information is available, return it. If not, return null.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:123

virtual void getSMSMutations(
    std::vector<
        std::unique_ptr<ScheduleDAGMutation>>&
        Mutations) const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:250

Parameters

std::vector<std::unique_ptr<ScheduleDAGMutation>>& Mutations

virtual const llvm::SelectionDAGTargetInfo*
getSelectionDAGInfo() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:100

virtual const llvm::TargetLowering*
getTargetLowering() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:99

virtual bool ignoreCSRForAllocationOrder(
    const llvm::MachineFunction& MF,
    unsigned int PhysReg) const

Description

True if the register allocator should use the allocation orders exactly as written in the tablegen descriptions, false if it should allocate the specified physical register later if is it callee-saved.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:306

Parameters

const llvm::MachineFunction& MF
unsigned int PhysReg

virtual bool isDependencyBreaking(
    const llvm::MachineInstr* MI,
    llvm::APInt& Mask) const

Description

Returns true if MI is a dependency breaking instruction for the subtarget. Similar in behavior to `isZeroIdiom`. However, it knows how to identify all dependency breaking instructions (i.e. not just zero-idioms). As for `isZeroIdiom`, this method returns a mask of "broken" dependencies. (See method `isZeroIdiom` for a detailed description of Mask).

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:165

Parameters

const llvm::MachineInstr* MI
llvm::APInt& Mask

virtual bool isOptimizableRegisterMove(
    const llvm::MachineInstr* MI) const

Description

Returns true if MI is a candidate for move elimination. A candidate for move elimination may be optimized out at register renaming stage. Subtargets can specify the set of optimizable moves by instantiating tablegen class `IsOptimizableRegisterMove` (see llvm/Target/TargetInstrPredicate.td). SubtargetEmitter is responsible for processing all the definitions of class IsOptimizableRegisterMove, and auto-generate an override for this method.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:178

Parameters

const llvm::MachineInstr* MI

virtual bool isXRaySupported() const

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:83

virtual bool isZeroIdiom(
    const llvm::MachineInstr* MI,
    llvm::APInt& Mask) const

Description

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget. This function also sets bits in Mask related to input operands that are not in a data dependency relationship. There is one bit for each machine operand; implicit operands follow explicit operands in the bit representation used for Mask. An empty (i.e. a mask with all bits cleared) means: data dependencies are "broken" for all the explicit input machine operands of MI.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:154

Parameters

const llvm::MachineInstr* MI
llvm::APInt& Mask

virtual void mirFileLoaded(
    llvm::MachineFunction& MF) const

Description

This is called after a .mir file was loaded.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:301

Parameters

llvm::MachineFunction& MF

virtual void overrideSchedPolicy(
    llvm::MachineSchedPolicy& Policy,
    unsigned int NumRegionInstrs) const

Description

Override generic scheduling policy within a region. This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic scheduling policy.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:224

Parameters

llvm::MachineSchedPolicy& Policy
unsigned int NumRegionInstrs

virtual unsigned int resolveSchedClass(
    unsigned int SchedClass,
    const llvm::MachineInstr* MI,
    const llvm::TargetSchedModel* SchedModel)
    const

Description

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:139

Parameters

unsigned int SchedClass
const llvm::MachineInstr* MI
const llvm::TargetSchedModel* SchedModel

virtual bool useAA() const

Description

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:277

virtual bool useDFAforSMS() const

Description

Default to DFA for resource management, return false when target will use ProcResource in InstrSchedModel instead.

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:256

~TargetSubtargetInfo()

Declared at: llvm/include/llvm/CodeGen/TargetSubtargetInfo.h:81