class TargetLowering

Declaration

class TargetLowering : public TargetLoweringBase { /* full declaration omitted */ };

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2953

Inherits from: TargetLoweringBase

Member Variables

Inherited from TargetLoweringBase:

protected GatherAllAliasesMaxDepth
protected MaxStoresPerMemset
protected MaxStoresPerMemsetOptSize
protected MaxStoresPerMemcpy
protected MaxStoresPerMemcpyOptSize
protected MaxGluedStoresPerMemcpy = 0
protected MaxLoadsPerMemcmp
protected MaxLoadsPerMemcmpOptSize
protected MaxStoresPerMemmove
protected MaxStoresPerMemmoveOptSize
protected PredictableSelectIsExpensive
protected EnableExtLdPromotion
protected IsStrictFPEnabled

Method Overview

public virtual void AdjustInstrPostInstrSelection(llvm::MachineInstr & MI, llvm::SDNode * Node) const
public llvm::SDValue BuildSDIV(llvm::SDNode * N, llvm::SelectionDAG & DAG, bool IsAfterLegalization, SmallVectorImpl<llvm::SDNode *> & Created) const
public virtual llvm::SDValue BuildSDIVPow2(llvm::SDNode * N, const llvm::APInt & Divisor, llvm::SelectionDAG & DAG, SmallVectorImpl<llvm::SDNode *> & Created) const
public llvm::SDValue BuildUDIV(llvm::SDNode * N, llvm::SelectionDAG & DAG, bool IsAfterLegalization, SmallVectorImpl<llvm::SDNode *> & Created) const
public virtual bool CanLowerReturn(CallingConv::ID, llvm::MachineFunction &, bool, const SmallVectorImpl<ISD::OutputArg> &, llvm::LLVMContext &) const
public virtual void ComputeConstraintToUse(llvm::TargetLowering::AsmOperandInfo & OpInfo, llvm::SDValue Op, llvm::SelectionDAG * DAG = nullptr) const
public virtual unsigned int ComputeNumSignBitsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedElts, const llvm::SelectionDAG & DAG, unsigned int Depth = 0) const
public virtual llvm::MachineBasicBlock * EmitInstrWithCustomInserter(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
public virtual bool ExpandInlineAsm(llvm::CallInst *) const
public virtual void HandleByVal(llvm::CCState *, unsigned int &, unsigned int) const
public llvm::SDValue IncrementMemoryAddress(llvm::SDValue Addr, llvm::SDValue Mask, const llvm::SDLoc & DL, llvm::EVT DataVT, llvm::SelectionDAG & DAG, bool IsCompressedMemory) const
public virtual bool IsDesirableToPromoteOp(llvm::SDValue, llvm::EVT &) const
public virtual void LowerAsmOperandForConstraint(llvm::SDValue Op, std::string & Constraint, int & Ops, llvm::SelectionDAG & DAG) const
public virtual llvm::SDValue LowerAsmOutputForConstraint(llvm::SDValue & Chain, llvm::SDValue & Flag, llvm::SDLoc DL, const llvm::TargetLowering::AsmOperandInfo & OpInfo, llvm::SelectionDAG & DAG) const
public virtual llvm::SDValue LowerCall(llvm::TargetLowering::CallLoweringInfo &, SmallVectorImpl<llvm::SDValue> &) const
public std::pair<SDValue, SDValue> LowerCallTo(llvm::TargetLowering::CallLoweringInfo & CLI) const
public virtual const llvm::MCExpr * LowerCustomJumpTableEntry(const llvm::MachineJumpTableInfo *, const llvm::MachineBasicBlock *, unsigned int, llvm::MCContext &) const
public virtual llvm::SDValue LowerFormalArguments(llvm::SDValue, CallingConv::ID, bool, const SmallVectorImpl<ISD::InputArg> &, const llvm::SDLoc &, llvm::SelectionDAG &, SmallVectorImpl<llvm::SDValue> &) const
public virtual llvm::SDValue LowerOperation(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
public virtual void LowerOperationWrapper(llvm::SDNode * N, SmallVectorImpl<llvm::SDValue> & Results, llvm::SelectionDAG & DAG) const
public virtual llvm::SDValue LowerReturn(llvm::SDValue, CallingConv::ID, bool, const SmallVectorImpl<ISD::OutputArg> &, const SmallVectorImpl<llvm::SDValue> &, const llvm::SDLoc &, llvm::SelectionDAG &) const
public virtual llvm::SDValue LowerToTLSEmulatedModel(const llvm::GlobalAddressSDNode * GA, llvm::SelectionDAG & DAG) const
public virtual const char * LowerXConstraint(llvm::EVT ConstraintVT) const
public int ParseConstraints(const llvm::DataLayout & DL, const llvm::TargetRegisterInfo * TRI, llvm::ImmutableCallSite CS) const
public virtual llvm::SDValue PerformDAGCombine(llvm::SDNode * N, llvm::TargetLowering::DAGCombinerInfo & DCI) const
public virtual void ReplaceNodeResults(llvm::SDNode *, SmallVectorImpl<llvm::SDValue> &, llvm::SelectionDAG &) const
public bool ShrinkDemandedConstant(llvm::SDValue Op, const llvm::APInt & Demanded, llvm::TargetLowering::TargetLoweringOpt & TLO) const
public bool ShrinkDemandedOp(llvm::SDValue Op, unsigned int BitWidth, const llvm::APInt & Demanded, llvm::TargetLowering::TargetLoweringOpt & TLO) const
public bool SimplifyDemandedBits(llvm::SDValue Op, const llvm::APInt & DemandedMask, llvm::TargetLowering::DAGCombinerInfo & DCI) const
public bool SimplifyDemandedBits(llvm::SDValue Op, const llvm::APInt & DemandedBits, llvm::KnownBits & Known, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth = 0, bool AssumeSingleUse = false) const
public bool SimplifyDemandedBits(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::KnownBits & Known, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth = 0, bool AssumeSingleUse = false) const
public virtual bool SimplifyDemandedBitsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::KnownBits & Known, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth = 0) const
public bool SimplifyDemandedVectorElts(llvm::SDValue Op, const llvm::APInt & DemandedEltMask, llvm::APInt & KnownUndef, llvm::APInt & KnownZero, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth = 0, bool AssumeSingleUse = false) const
public bool SimplifyDemandedVectorElts(llvm::SDValue Op, const llvm::APInt & DemandedElts, llvm::APInt & KnownUndef, llvm::APInt & KnownZero, llvm::TargetLowering::DAGCombinerInfo & DCI) const
public virtual bool SimplifyDemandedVectorEltsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedElts, llvm::APInt & KnownUndef, llvm::APInt & KnownZero, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth = 0) const
public llvm::SDValue SimplifyMultipleUseDemandedBits(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::SelectionDAG & DAG, unsigned int Depth) const
public virtual llvm::SDValue SimplifyMultipleUseDemandedBitsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::SelectionDAG & DAG, unsigned int Depth) const
public llvm::SDValue SimplifySetCC(llvm::EVT VT, llvm::SDValue N0, llvm::SDValue N1, ISD::CondCode Cond, bool foldBooleans, llvm::TargetLowering::DAGCombinerInfo & DCI, const llvm::SDLoc & dl) const
public TargetLowering(const llvm::TargetMachine & TM)
public TargetLowering(const llvm::TargetLowering &)
public llvm::SDValue buildLegalVectorShuffle(llvm::EVT VT, const llvm::SDLoc & DL, llvm::SDValue N0, llvm::SDValue N1, MutableArrayRef<int> Mask, llvm::SelectionDAG & DAG) const
public virtual unsigned int combineRepeatedFPDivisors() const
public virtual void computeKnownBitsForFrameIndex(const llvm::SDValue FIOp, llvm::KnownBits & Known, const llvm::APInt & DemandedElts, const llvm::SelectionDAG & DAG, unsigned int Depth = 0) const
public virtual void computeKnownBitsForTargetInstr(llvm::GISelKnownBits & Analysis, llvm::Register R, llvm::KnownBits & Known, const llvm::APInt & DemandedElts, const llvm::MachineRegisterInfo & MRI, unsigned int Depth = 0) const
public virtual void computeKnownBitsForTargetNode(const llvm::SDValue Op, llvm::KnownBits & Known, const llvm::APInt & DemandedElts, const llvm::SelectionDAG & DAG, unsigned int Depth = 0) const
public virtual llvm::FastISel * createFastISel(llvm::FunctionLoweringInfo &, const llvm::TargetLibraryInfo *) const
public virtual llvm::SDValue emitStackGuardXorFP(llvm::SelectionDAG & DAG, llvm::SDValue Val, const llvm::SDLoc & DL) const
public bool expandABS(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public llvm::SDValue expandAddSubSat(llvm::SDNode * Node, llvm::SelectionDAG & DAG) const
public bool expandCTLZ(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public bool expandCTPOP(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public bool expandCTTZ(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public llvm::SDValue expandFMINNUM_FMAXNUM(llvm::SDNode * N, llvm::SelectionDAG & DAG) const
public bool expandFP_TO_SINT(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public bool expandFP_TO_UINT(llvm::SDNode * N, llvm::SDValue & Result, llvm::SDValue & Chain, llvm::SelectionDAG & DAG) const
public llvm::SDValue expandFixedPointDiv(unsigned int Opcode, const llvm::SDLoc & dl, llvm::SDValue LHS, llvm::SDValue RHS, unsigned int Scale, llvm::SelectionDAG & DAG) const
public llvm::SDValue expandFixedPointMul(llvm::SDNode * Node, llvm::SelectionDAG & DAG) const
public bool expandFunnelShift(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public virtual llvm::SDValue expandIndirectJTBranch(const llvm::SDLoc & dl, llvm::SDValue Value, llvm::SDValue Addr, llvm::SelectionDAG & DAG) const
public bool expandMUL(llvm::SDNode * N, llvm::SDValue & Lo, llvm::SDValue & Hi, llvm::EVT HiLoVT, llvm::SelectionDAG & DAG, llvm::TargetLoweringBase::MulExpansionKind Kind, llvm::SDValue LL = llvm::SDValue(), llvm::SDValue LH = llvm::SDValue(), llvm::SDValue RL = llvm::SDValue(), llvm::SDValue RH = llvm::SDValue()) const
public bool expandMULO(llvm::SDNode * Node, llvm::SDValue & Result, llvm::SDValue & Overflow, llvm::SelectionDAG & DAG) const
public bool expandMUL_LOHI(unsigned int Opcode, llvm::EVT VT, llvm::SDLoc dl, llvm::SDValue LHS, llvm::SDValue RHS, SmallVectorImpl<llvm::SDValue> & Result, llvm::EVT HiLoVT, llvm::SelectionDAG & DAG, llvm::TargetLoweringBase::MulExpansionKind Kind, llvm::SDValue LL = llvm::SDValue(), llvm::SDValue LH = llvm::SDValue(), llvm::SDValue RL = llvm::SDValue(), llvm::SDValue RH = llvm::SDValue()) const
public bool expandROT(llvm::SDNode * N, llvm::SDValue & Result, llvm::SelectionDAG & DAG) const
public void expandSADDSUBO(llvm::SDNode * Node, llvm::SDValue & Result, llvm::SDValue & Overflow, llvm::SelectionDAG & DAG) const
public void expandUADDSUBO(llvm::SDNode * Node, llvm::SDValue & Result, llvm::SDValue & Overflow, llvm::SelectionDAG & DAG) const
public bool expandUINT_TO_FP(llvm::SDNode * N, llvm::SDValue & Result, llvm::SDValue & Chain, llvm::SelectionDAG & DAG) const
public std::pair<SDValue, SDValue> expandUnalignedLoad(llvm::LoadSDNode * LD, llvm::SelectionDAG & DAG) const
public llvm::SDValue expandUnalignedStore(llvm::StoreSDNode * ST, llvm::SelectionDAG & DAG) const
public llvm::SDValue expandVecReduce(llvm::SDNode * Node, llvm::SelectionDAG & DAG) const
public bool findOptimalMemOpLowering(int & MemOps, unsigned int Limit, uint64_t Size, unsigned int DstAlign, unsigned int SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, bool AllowOverlap, unsigned int DstAS, unsigned int SrcAS, const llvm::AttributeList & FuncAttributes) const
public virtual bool functionArgumentNeedsConsecutiveRegisters(llvm::Type * Ty, CallingConv::ID CallConv, bool isVarArg) const
public virtual const char * getClearCacheBuiltinName() const
public virtual llvm::TargetLowering::ConstraintType getConstraintType(llvm::StringRef Constraint) const
public virtual unsigned int getInlineAsmMemConstraint(llvm::StringRef ConstraintCode) const
public virtual unsigned int getJumpTableEncoding() const
public virtual MachineMemOperand::Flags getMMOFlags(const llvm::Instruction & I) const
public virtual llvm::TargetLowering::ConstraintWeight getMultipleConstraintMatchWeight(llvm::TargetLowering::AsmOperandInfo & info, int maIndex) const
public virtual llvm::SDValue getNegatedExpression(llvm::SDValue Op, llvm::SelectionDAG & DAG, bool LegalOperations, bool ForCodeSize, unsigned int Depth = 0) const
public virtual llvm::SDValue getPICJumpTableRelocBase(llvm::SDValue Table, llvm::SelectionDAG & DAG) const
public virtual const llvm::MCExpr * getPICJumpTableRelocBaseExpr(const llvm::MachineFunction * MF, unsigned int JTI, llvm::MCContext & Ctx) const
public virtual bool getPostIndexedAddressParts(llvm::SDNode *, llvm::SDNode *, llvm::SDValue &, llvm::SDValue &, ISD::MemIndexedMode &, llvm::SelectionDAG &) const
public virtual bool getPreIndexedAddressParts(llvm::SDNode *, llvm::SDValue &, llvm::SDValue &, ISD::MemIndexedMode &, llvm::SelectionDAG &) const
public virtual llvm::SDValue getRecipEstimate(llvm::SDValue Operand, llvm::SelectionDAG & DAG, int Enabled, int & RefinementSteps) const
public virtual std::pair<unsigned int, const TargetRegisterClass *> getRegForInlineAsmConstraint(const llvm::TargetRegisterInfo * TRI, llvm::StringRef Constraint, llvm::MVT VT) const
public virtual llvm::Register getRegisterByName(const char * RegName, llvm::LLT Ty, const llvm::MachineFunction & MF) const
public virtual const llvm::MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
public virtual llvm::TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(llvm::TargetLowering::AsmOperandInfo & info, const char * constraint) const
public virtual llvm::SDValue getSqrtEstimate(llvm::SDValue Operand, llvm::SelectionDAG & DAG, int Enabled, int & RefinementSteps, bool & UseOneConstNR, bool Reciprocal) const
public virtual const llvm::Constant * getTargetConstantFromLoad(llvm::LoadSDNode * LD) const
public virtual const char * getTargetNodeName(unsigned int Opcode) const
public virtual llvm::EVT getTypeForExtReturn(llvm::LLVMContext & Context, llvm::EVT VT, ISD::NodeType) const
public llvm::SDValue getVectorElementPointer(llvm::SelectionDAG & DAG, llvm::SDValue VecPtr, llvm::EVT VecVT, llvm::SDValue Index) const
public virtual void initializeSplitCSR(llvm::MachineBasicBlock * Entry) const
public virtual void insertCopiesSplitCSR(llvm::MachineBasicBlock * Entry, const SmallVectorImpl<llvm::MachineBasicBlock *> & Exits) const
public bool isConstFalseVal(const llvm::SDNode * N) const
public bool isConstTrueVal(const llvm::SDNode * N) const
public virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef<int> ShuffleMask, llvm::EVT SrcVT, llvm::EVT TruncVT) const
public virtual bool isDesirableToCommuteWithShift(const llvm::SDNode * N, llvm::CombineLevel Level) const
public virtual bool isDesirableToTransformToIntegerOp(unsigned int, llvm::EVT) const
public bool isExtendedTrueVal(const llvm::ConstantSDNode * N, llvm::EVT VT, bool SExt) const
public virtual bool isGAPlusOffset(llvm::SDNode * N, const llvm::GlobalValue *& GA, int64_t & Offset) const
public bool isInTailCallPosition(llvm::SelectionDAG & DAG, llvm::SDNode * Node, llvm::SDValue & Chain) const
public virtual bool isIndexingLegal(llvm::MachineInstr & MI, llvm::Register Base, llvm::Register Offset, bool IsPre, llvm::MachineRegisterInfo & MRI) const
public virtual bool isKnownNeverNaNForTargetNode(llvm::SDValue Op, const llvm::SelectionDAG & DAG, bool SNaN = false, unsigned int Depth = 0) const
public virtual char isNegatibleForFree(llvm::SDValue Op, llvm::SelectionDAG & DAG, bool LegalOperations, bool ForCodeSize, unsigned int Depth = 0) const
public virtual bool isOffsetFoldingLegal(const llvm::GlobalAddressSDNode * GA) const
public bool isPositionIndependent() const
public virtual bool isSDNodeAlwaysUniform(const llvm::SDNode * N) const
public virtual bool isSDNodeSourceOfDivergence(const llvm::SDNode * N, llvm::FunctionLoweringInfo * FLI, llvm::LegacyDivergenceAnalysis * DA) const
public virtual bool isTypeDesirableForOp(unsigned int, llvm::EVT VT) const
public virtual bool isUsedByReturnOnly(llvm::SDNode *, llvm::SDValue &) const
public virtual bool lowerAtomicLoadAsLoadSDNode(const llvm::LoadInst & LI) const
public virtual bool lowerAtomicStoreAsStoreSDNode(const llvm::StoreInst & SI) const
public llvm::SDValue lowerCmpEqZeroToCtlzSrl(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
public std::pair<SDValue, SDValue> makeLibCall(llvm::SelectionDAG & DAG, RTLIB::Libcall LC, llvm::EVT RetVT, ArrayRef<llvm::SDValue> Ops, llvm::TargetLowering::MakeLibCallOptions CallOptions, const llvm::SDLoc & dl, llvm::SDValue Chain = llvm::SDValue()) const
public virtual bool mayBeEmittedAsTailCall(const llvm::CallInst *) const
public bool parametersInCSRMatch(const llvm::MachineRegisterInfo & MRI, const uint32_t * CallerPreservedMask, const SmallVectorImpl<llvm::CCValAssign> & ArgLocs, const SmallVectorImpl<llvm::SDValue> & OutVals) const
public virtual llvm::SDValue prepareVolatileOrAtomicLoad(llvm::SDValue Chain, const llvm::SDLoc & DL, llvm::SelectionDAG & DAG) const
public std::pair<SDValue, SDValue> scalarizeVectorLoad(llvm::LoadSDNode * LD, llvm::SelectionDAG & DAG) const
public llvm::SDValue scalarizeVectorStore(llvm::StoreSDNode * ST, llvm::SelectionDAG & DAG) const
public virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const llvm::DataLayout & DL) const
public void softenSetCCOperands(llvm::SelectionDAG & DAG, llvm::EVT VT, llvm::SDValue & NewLHS, llvm::SDValue & NewRHS, ISD::CondCode & CCCode, const llvm::SDLoc & DL, const llvm::SDValue OldLHS, const llvm::SDValue OldRHS, llvm::SDValue & Chain, bool IsSignaling = false) const
public void softenSetCCOperands(llvm::SelectionDAG & DAG, llvm::EVT VT, llvm::SDValue & NewLHS, llvm::SDValue & NewRHS, ISD::CondCode & CCCode, const llvm::SDLoc & DL, const llvm::SDValue OldLHS, const llvm::SDValue OldRHS) const
public virtual bool supportSplitCSR(llvm::MachineFunction * MF) const
public virtual bool supportSwiftError() const
public virtual bool targetShrinkDemandedConstant(llvm::SDValue Op, const llvm::APInt & Demanded, llvm::TargetLowering::TargetLoweringOpt & TLO) const
public virtual llvm::SDValue unwrapAddress(llvm::SDValue N) const
public virtual bool useLoadStackGuardNode() const
public bool verifyReturnAddressArgumentIsConstant(llvm::SDValue Op, llvm::SelectionDAG & DAG) const

Inherited from TargetLoweringBase:

Methods

¶virtual void AdjustInstrPostInstrSelection(
    llvm::MachineInstr& MI,
    llvm::SDNode* Node) const

Description

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4235

Parameters

llvm::MachineInstr& MI
llvm::SDNode* Node

¶llvm::SDValue BuildSDIV(
    llvm::SDNode* N,
    llvm::SelectionDAG& DAG,
    bool IsAfterLegalization,
    SmallVectorImpl<llvm::SDNode*>& Created) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3983

Parameters

llvm::SDNode* N
llvm::SelectionDAG& DAG
bool IsAfterLegalization
SmallVectorImpl<llvm::SDNode*>& Created

¶virtual llvm::SDValue BuildSDIVPow2(
    llvm::SDNode* N,
    const llvm::APInt& Divisor,
    llvm::SelectionDAG& DAG,
    SmallVectorImpl<llvm::SDNode*>& Created) const

Description

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. If the target returns an empty SDValue, LLVM assumes SDIV is expensive and replaces it with a series of other integer operations.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3992

Parameters

llvm::SDNode* N
const llvm::APInt& Divisor
llvm::SelectionDAG& DAG
SmallVectorImpl<llvm::SDNode*>& Created

¶llvm::SDValue BuildUDIV(
    llvm::SDNode* N,
    llvm::SelectionDAG& DAG,
    bool IsAfterLegalization,
    SmallVectorImpl<llvm::SDNode*>& Created) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3985

Parameters

llvm::SDNode* N
llvm::SelectionDAG& DAG
bool IsAfterLegalization
SmallVectorImpl<llvm::SDNode*>& Created

¶virtual bool CanLowerReturn(
    CallingConv::ID,
    llvm::MachineFunction&,
    bool,
    const SmallVectorImpl<ISD::OutputArg>&,
    llvm::LLVMContext&) const

Description

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. If false is returned, an sret-demotion is performed.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3667

Parameters

CallingConv::ID
llvm::MachineFunction&
bool
const SmallVectorImpl<ISD::OutputArg>&
llvm::LLVMContext&

¶virtual void ComputeConstraintToUse(
    llvm::TargetLowering::AsmOperandInfo& OpInfo,
    llvm::SDValue Op,
    llvm::SelectionDAG* DAG = nullptr) const

Description

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3937

Parameters

llvm::TargetLowering::AsmOperandInfo& OpInfo
llvm::SDValue Op
llvm::SelectionDAG* DAG = nullptr

¶virtual unsigned int
ComputeNumSignBitsForTargetNode(
    llvm::SDValue Op,
    const llvm::APInt& DemandedElts,
    const llvm::SelectionDAG& DAG,
    unsigned int Depth = 0) const

Description

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner. The DemandedElts argument allows us to only collect the minimum sign bits that are shared by the requested vector elements.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3217

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedElts
const llvm::SelectionDAG& DAG
unsigned int Depth = 0

¶virtual llvm::MachineBasicBlock*
EmitInstrWithCustomInserter(
    llvm::MachineInstr& MI,
    llvm::MachineBasicBlock* MBB) const

Description

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of \p MBB.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4229

Parameters

llvm::MachineInstr& MI
llvm::MachineBasicBlock* MBB

¶virtual bool ExpandInlineAsm(
    llvm::CallInst*) const

Description

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3852

Parameters

llvm::CallInst*

¶virtual void HandleByVal(llvm::CCState*,
                         unsigned int&,
                         unsigned int) const

Description

Target-specific cleanup for formal ByVal parameters.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3662

Parameters

llvm::CCState*
unsigned int&
unsigned int

¶llvm::SDValue IncrementMemoryAddress(
    llvm::SDValue Addr,
    llvm::SDValue Mask,
    const llvm::SDLoc& DL,
    llvm::EVT DataVT,
    llvm::SelectionDAG& DAG,
    bool IsCompressedMemory) const

Description

Increments memory address \p Addr according to the type of the value\p DataVT that should be stored. If the data is stored in compressed form, the memory address should be incremented according to the number of the stored elements. This number is equal to the number of '1's bits in the \p Mask. \p DataVT is a vector type. \p Mask is a vector value.\p DataVT and \p Mask have the same number of vector elements.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4170

Parameters

llvm::SDValue Addr
llvm::SDValue Mask
const llvm::SDLoc& DL
llvm::EVT DataVT
llvm::SelectionDAG& DAG
bool IsCompressedMemory

¶virtual bool IsDesirableToPromoteOp(
    llvm::SDValue,
    llvm::EVT&) const

Description

This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3383

Parameters

llvm::SDValue
llvm::EVT&

¶virtual void LowerAsmOperandForConstraint(
    llvm::SDValue Op,
    std::string& Constraint,
    int& Ops,
    llvm::SelectionDAG& DAG) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3970

Parameters

llvm::SDValue Op
std::string& Constraint
int& Ops
llvm::SelectionDAG& DAG

¶virtual llvm::SDValue LowerAsmOutputForConstraint(
    llvm::SDValue& Chain,
    llvm::SDValue& Flag,
    llvm::SDLoc DL,
    const llvm::TargetLowering::AsmOperandInfo&
        OpInfo,
    llvm::SelectionDAG& DAG) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3975

Parameters

llvm::SDValue& Chain
llvm::SDValue& Flag
llvm::SDLoc DL
const llvm::TargetLowering::AsmOperandInfo& OpInfo
llvm::SelectionDAG& DAG

¶virtual llvm::SDValue LowerCall(
    llvm::TargetLowering::CallLoweringInfo&,
    SmallVectorImpl<llvm::SDValue>&) const

Description

This hook must be implemented to lower calls into the specified DAG. The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3656

Parameters

llvm::TargetLowering::CallLoweringInfo&
SmallVectorImpl<llvm::SDValue>&

¶std::pair<SDValue, SDValue> LowerCallTo(
    llvm::TargetLowering::CallLoweringInfo& CLI)
    const

Description

This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3648

Parameters

llvm::TargetLowering::CallLoweringInfo& CLI

¶virtual const llvm::MCExpr*
LowerCustomJumpTableEntry(
    const llvm::MachineJumpTableInfo*,
    const llvm::MachineBasicBlock*,
    unsigned int,
    llvm::MCContext&) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3009

Parameters

const llvm::MachineJumpTableInfo*
const llvm::MachineBasicBlock*
unsigned int
llvm::MCContext&

¶virtual llvm::SDValue LowerFormalArguments(
    llvm::SDValue,
    CallingConv::ID,
    bool,
    const SmallVectorImpl<ISD::InputArg>&,
    const llvm::SDLoc&,
    llvm::SelectionDAG&,
    SmallVectorImpl<llvm::SDValue>&) const

Description

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3437

Parameters

llvm::SDValue
CallingConv::ID
bool
const SmallVectorImpl<ISD::InputArg>&
const llvm::SDLoc&
llvm::SelectionDAG&
SmallVectorImpl<llvm::SDValue>&

¶virtual llvm::SDValue LowerOperation(
    llvm::SDValue Op,
    llvm::SelectionDAG& DAG) const

Description

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal. If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3814

Parameters

llvm::SDValue Op
llvm::SelectionDAG& DAG

¶virtual void LowerOperationWrapper(
    llvm::SDNode* N,
    SmallVectorImpl<llvm::SDValue>& Results,
    llvm::SelectionDAG& DAG) const

Description

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback. TODO: Consider merging with ReplaceNodeResults. The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3805

Parameters

llvm::SDNode* N
SmallVectorImpl<llvm::SDValue>& Results
llvm::SelectionDAG& DAG

¶virtual llvm::SDValue LowerReturn(
    llvm::SDValue,
    CallingConv::ID,
    bool,
    const SmallVectorImpl<ISD::OutputArg>&,
    const SmallVectorImpl<llvm::SDValue>&,
    const llvm::SDLoc&,
    llvm::SelectionDAG&) const

Description

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. The implementation should return the resulting token chain value.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3679

Parameters

llvm::SDValue
CallingConv::ID
bool
const SmallVectorImpl<ISD::OutputArg>&
const SmallVectorImpl<llvm::SDValue>&
const llvm::SDLoc&
llvm::SelectionDAG&

¶virtual llvm::SDValue LowerToTLSEmulatedModel(
    const llvm::GlobalAddressSDNode* GA,
    llvm::SelectionDAG& DAG) const

Description

Lower TLS global address SDNode for target independent emulated TLS model.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4250

Parameters

const llvm::GlobalAddressSDNode* GA
llvm::SelectionDAG& DAG

¶virtual const char* LowerXConstraint(
    llvm::EVT ConstraintVT) const

Description

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3966

Parameters

llvm::EVT ConstraintVT

¶int ParseConstraints(
    const llvm::DataLayout& DL,
    const llvm::TargetRegisterInfo* TRI,
    llvm::ImmutableCallSite CS) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3919

Parameters

const llvm::DataLayout& DL
const llvm::TargetRegisterInfo* TRI
llvm::ImmutableCallSite CS

¶virtual llvm::SDValue PerformDAGCombine(
    llvm::SDNode* N,
    llvm::TargetLowering::DAGCombinerInfo& DCI)
    const

Description

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand. In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3334

Parameters

llvm::SDNode* N
llvm::TargetLowering::DAGCombinerInfo& DCI

¶virtual void ReplaceNodeResults(
    llvm::SDNode*,
    SmallVectorImpl<llvm::SDValue>&,
    llvm::SelectionDAG&) const

Description

This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type. The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3825

Parameters

llvm::SDNode*
SmallVectorImpl<llvm::SDValue>&
llvm::SelectionDAG&

¶bool ShrinkDemandedConstant(
    llvm::SDValue Op,
    const llvm::APInt& Demanded,
    llvm::TargetLowering::TargetLoweringOpt& TLO)
    const

Description

Check to see if the specified operand of the specified instruction is a constant integer. If so, check to see if there are any bits set in the constant that are not demanded. If so, shrink the constant and return true.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3105

Parameters

llvm::SDValue Op
const llvm::APInt& Demanded
llvm::TargetLowering::TargetLoweringOpt& TLO

¶bool ShrinkDemandedOp(
    llvm::SDValue Op,
    unsigned int BitWidth,
    const llvm::APInt& Demanded,
    llvm::TargetLowering::TargetLoweringOpt& TLO)
    const

Description

Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be generalized for targets with other types of implicit widening casts.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3119

Parameters

llvm::SDValue Op
unsigned int BitWidth
const llvm::APInt& Demanded
llvm::TargetLowering::TargetLoweringOpt& TLO

¶bool SimplifyDemandedBits(
    llvm::SDValue Op,
    const llvm::APInt& DemandedMask,
    llvm::TargetLowering::DAGCombinerInfo& DCI)
    const

Description

Helper wrapper around SimplifyDemandedBits. Adds Op back to the worklist upon success.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3149

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedMask
llvm::TargetLowering::DAGCombinerInfo& DCI

¶bool SimplifyDemandedBits(
    llvm::SDValue Op,
    const llvm::APInt& DemandedBits,
    llvm::KnownBits& Known,
    llvm::TargetLowering::TargetLoweringOpt& TLO,
    unsigned int Depth = 0,
    bool AssumeSingleUse = false) const

Description

Helper wrapper around SimplifyDemandedBits, demanding all elements. Adds Op back to the worklist upon success.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3142

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedBits
llvm::KnownBits& Known
llvm::TargetLowering::TargetLoweringOpt& TLO
unsigned int Depth = 0
bool AssumeSingleUse = false

¶bool SimplifyDemandedBits(
    llvm::SDValue Op,
    const llvm::APInt& DemandedBits,
    const llvm::APInt& DemandedElts,
    llvm::KnownBits& Known,
    llvm::TargetLowering::TargetLoweringOpt& TLO,
    unsigned int Depth = 0,
    bool AssumeSingleUse = false) const

Description

Look at Op. At this point, we know that only the DemandedBits bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the Demanded masks.\p AssumeSingleUse When this parameter is true, this function will attempt to simplify \p Op even if there are multiple uses. Callers are responsible for correctly updating the DAG based on the results of this function, because simply replacing replacing TLO.Old with TLO.New will be incorrect when this parameter is true and TLO.Old has multiple uses.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3135

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedBits
const llvm::APInt& DemandedElts
llvm::KnownBits& Known
llvm::TargetLowering::TargetLoweringOpt& TLO
unsigned int Depth = 0
bool AssumeSingleUse = false

¶virtual bool SimplifyDemandedBitsForTargetNode(
    llvm::SDValue Op,
    const llvm::APInt& DemandedBits,
    const llvm::APInt& DemandedElts,
    llvm::KnownBits& Known,
    llvm::TargetLowering::TargetLoweringOpt& TLO,
    unsigned int Depth = 0) const

Description

Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the Demanded masks.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3236

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedBits
const llvm::APInt& DemandedElts
llvm::KnownBits& Known
llvm::TargetLowering::TargetLoweringOpt& TLO
unsigned int Depth = 0

¶bool SimplifyDemandedVectorElts(
    llvm::SDValue Op,
    const llvm::APInt& DemandedEltMask,
    llvm::APInt& KnownUndef,
    llvm::APInt& KnownZero,
    llvm::TargetLowering::TargetLoweringOpt& TLO,
    unsigned int Depth = 0,
    bool AssumeSingleUse = false) const

Description

Look at Vector Op. At this point, we know that only the DemandedElts elements of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, storing the original and new nodes in TLO. Otherwise, analyze the expression and return a mask of KnownUndef and KnownZero elements for the expression (used to simplify the caller). The KnownUndef/Zero elements may only be accurate for those bits in the DemandedMask.\p AssumeSingleUse When this parameter is true, this function will attempt to simplify \p Op even if there are multiple uses. Callers are responsible for correctly updating the DAG based on the results of this function, because simply replacing replacing TLO.Old with TLO.New will be incorrect when this parameter is true and TLO.Old has multiple uses.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3174

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedEltMask
llvm::APInt& KnownUndef
llvm::APInt& KnownZero
llvm::TargetLowering::TargetLoweringOpt& TLO
unsigned int Depth = 0
bool AssumeSingleUse = false

¶bool SimplifyDemandedVectorElts(
    llvm::SDValue Op,
    const llvm::APInt& DemandedElts,
    llvm::APInt& KnownUndef,
    llvm::APInt& KnownZero,
    llvm::TargetLowering::DAGCombinerInfo& DCI)
    const

Description

Helper wrapper around SimplifyDemandedVectorElts. Adds Op back to the worklist upon success.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3181

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedElts
llvm::APInt& KnownUndef
llvm::APInt& KnownZero
llvm::TargetLowering::DAGCombinerInfo& DCI

¶virtual bool
SimplifyDemandedVectorEltsForTargetNode(
    llvm::SDValue Op,
    const llvm::APInt& DemandedElts,
    llvm::APInt& KnownUndef,
    llvm::APInt& KnownZero,
    llvm::TargetLowering::TargetLoweringOpt& TLO,
    unsigned int Depth = 0) const

Description

Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. Otherwise, analyze the expression and return a mask of KnownUndef and KnownZero elements for the expression (used to simplify the caller). The KnownUndef/Zero elements may only be accurate for those bits in the DemandedMask.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3227

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedElts
llvm::APInt& KnownUndef
llvm::APInt& KnownZero
llvm::TargetLowering::TargetLoweringOpt& TLO
unsigned int Depth = 0

¶llvm::SDValue SimplifyMultipleUseDemandedBits(
    llvm::SDValue Op,
    const llvm::APInt& DemandedBits,
    const llvm::APInt& DemandedElts,
    llvm::SelectionDAG& DAG,
    unsigned int Depth) const

Description

More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3155

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedBits
const llvm::APInt& DemandedElts
llvm::SelectionDAG& DAG
unsigned int Depth

¶virtual llvm::SDValue
SimplifyMultipleUseDemandedBitsForTargetNode(
    llvm::SDValue Op,
    const llvm::APInt& DemandedBits,
    const llvm::APInt& DemandedElts,
    llvm::SelectionDAG& DAG,
    unsigned int Depth) const

Description

More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3246

Parameters

llvm::SDValue Op
const llvm::APInt& DemandedBits
const llvm::APInt& DemandedElts
llvm::SelectionDAG& DAG
unsigned int Depth

¶llvm::SDValue SimplifySetCC(
    llvm::EVT VT,
    llvm::SDValue N0,
    llvm::SDValue N1,
    ISD::CondCode Cond,
    bool foldBooleans,
    llvm::TargetLowering::DAGCombinerInfo& DCI,
    const llvm::SDLoc& dl) const

Description

Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3309

Parameters

llvm::EVT VT
llvm::SDValue N0
llvm::SDValue N1
ISD::CondCode Cond
bool foldBooleans
llvm::TargetLowering::DAGCombinerInfo& DCI
const llvm::SDLoc& dl

¶TargetLowering(const llvm::TargetMachine& TM)

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2961

Parameters

const llvm::TargetMachine& TM

¶TargetLowering(const llvm::TargetLowering&)

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2958

Parameters

const llvm::TargetLowering&

¶llvm::SDValue buildLegalVectorShuffle(
    llvm::EVT VT,
    const llvm::SDLoc& DL,
    llvm::SDValue N0,
    llvm::SDValue N1,
    MutableArrayRef<int> Mask,
    llvm::SelectionDAG& DAG) const

Description

Tries to build a legal vector shuffle using the provided parameters or equivalent variations. The Mask argument maybe be modified as the function tries different variations. Returns an empty SDValue if the operation fails.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3254

Parameters

llvm::EVT VT
const llvm::SDLoc& DL
llvm::SDValue N0
llvm::SDValue N1
MutableArrayRef<int> Mask
llvm::SelectionDAG& DAG

¶virtual unsigned int combineRepeatedFPDivisors()
    const

Description

Indicate whether this target prefers to combine FDIVs with the same divisor. If the transform should never be done, return zero. If the transform should be done, return the minimum number of divisor uses that must exist.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4000

¶virtual void computeKnownBitsForFrameIndex(
    const llvm::SDValue FIOp,
    llvm::KnownBits& Known,
    const llvm::APInt& DemandedElts,
    const llvm::SelectionDAG& DAG,
    unsigned int Depth = 0) const

Description

Determine which of the bits of FrameIndex \p FIOp are known to be 0. Default implementation computes low bits based on alignment information. This should preserve known bits passed into it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3207

Parameters

const llvm::SDValue FIOp
llvm::KnownBits& Known
const llvm::APInt& DemandedElts
const llvm::SelectionDAG& DAG
unsigned int Depth = 0

¶virtual void computeKnownBitsForTargetInstr(
    llvm::GISelKnownBits& Analysis,
    llvm::Register R,
    llvm::KnownBits& Known,
    const llvm::APInt& DemandedElts,
    const llvm::MachineRegisterInfo& MRI,
    unsigned int Depth = 0) const

Description

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. This is for GISel.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3198

Parameters

llvm::GISelKnownBits& Analysis
llvm::Register R
llvm::KnownBits& Known
const llvm::APInt& DemandedElts
const llvm::MachineRegisterInfo& MRI
unsigned int Depth = 0

¶virtual void computeKnownBitsForTargetNode(
    const llvm::SDValue Op,
    llvm::KnownBits& Known,
    const llvm::APInt& DemandedElts,
    const llvm::SelectionDAG& DAG,
    unsigned int Depth = 0) const

Description

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3189

Parameters

const llvm::SDValue Op
llvm::KnownBits& Known
const llvm::APInt& DemandedElts
const llvm::SelectionDAG& DAG
unsigned int Depth = 0

¶virtual llvm::FastISel* createFastISel(
    llvm::FunctionLoweringInfo&,
    const llvm::TargetLibraryInfo*) const

Description

This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3836

Parameters

llvm::FunctionLoweringInfo&
const llvm::TargetLibraryInfo*

¶virtual llvm::SDValue emitStackGuardXorFP(
    llvm::SelectionDAG& DAG,
    llvm::SDValue Val,
    const llvm::SDLoc& DL) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4244

Parameters

llvm::SelectionDAG& DAG
llvm::SDValue Val
const llvm::SDLoc& DL

¶bool expandABS(llvm::SDNode* N,
               llvm::SDValue& Result,
               llvm::SelectionDAG& DAG) const

Description

Expand ABS nodes. Expands vector/scalar ABS nodes, vector nodes can only succeed if all operations are legal/custom. (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4141

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶llvm::SDValue expandAddSubSat(
    llvm::SDNode* Node,
    llvm::SelectionDAG& DAG) const

Description

Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This method accepts integers as its arguments.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4183

Parameters

llvm::SDNode* Node
llvm::SelectionDAG& DAG

¶bool expandCTLZ(llvm::SDNode* N,
                llvm::SDValue& Result,
                llvm::SelectionDAG& DAG) const

Description

Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes, vector nodes can only succeed if all operations are legal/custom.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4126

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶bool expandCTPOP(llvm::SDNode* N,
                 llvm::SDValue& Result,
                 llvm::SelectionDAG& DAG) const

Description

Expand CTPOP nodes. Expands vector/scalar CTPOP nodes, vector nodes can only succeed if all operations are legal/custom.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4119

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶bool expandCTTZ(llvm::SDNode* N,
                llvm::SDValue& Result,
                llvm::SelectionDAG& DAG) const

Description

Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes, vector nodes can only succeed if all operations are legal/custom.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4133

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶llvm::SDValue expandFMINNUM_FMAXNUM(
    llvm::SDNode* N,
    llvm::SelectionDAG& DAG) const

Description

Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4112

Parameters

llvm::SDNode* N
llvm::SelectionDAG& DAG

¶bool expandFP_TO_SINT(
    llvm::SDNode* N,
    llvm::SDValue& Result,
    llvm::SelectionDAG& DAG) const

Description

Expand float(f32) to SINT(i64) conversion

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4093

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶bool expandFP_TO_UINT(
    llvm::SDNode* N,
    llvm::SDValue& Result,
    llvm::SDValue& Chain,
    llvm::SelectionDAG& DAG) const

Description

Expand float to UINT conversion

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4100

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SDValue& Chain: output chain after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶llvm::SDValue expandFixedPointDiv(
    unsigned int Opcode,
    const llvm::SDLoc& dl,
    llvm::SDValue LHS,
    llvm::SDValue RHS,
    unsigned int Scale,
    llvm::SelectionDAG& DAG) const

Description

Method for building the DAG expansion of ISD::[US]DIVFIX. This method accepts integers as its arguments. Note: This method may fail if the division could not be performed within the type. Clients must retry with a wider type if this happens.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4193

Parameters

unsigned int Opcode
const llvm::SDLoc& dl
llvm::SDValue LHS
llvm::SDValue RHS
unsigned int Scale
llvm::SelectionDAG& DAG

¶llvm::SDValue expandFixedPointMul(
    llvm::SDNode* Node,
    llvm::SelectionDAG& DAG) const

Description

Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This method accepts integers as its arguments.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4187

Parameters

llvm::SDNode* Node
llvm::SelectionDAG& DAG

¶bool expandFunnelShift(
    llvm::SDNode* N,
    llvm::SDValue& Result,
    llvm::SelectionDAG& DAG) const

Description

Expand funnel shift.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4081

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶virtual llvm::SDValue expandIndirectJTBranch(
    const llvm::SDLoc& dl,
    llvm::SDValue Value,
    llvm::SDValue Addr,
    llvm::SelectionDAG& DAG) const

Description

Expands target specific indirect branch for the case of JumpTable expanasion.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4255

Parameters

const llvm::SDLoc& dl
llvm::SDValue Value
llvm::SDValue Addr
llvm::SelectionDAG& DAG

¶bool expandMUL(
    llvm::SDNode* N,
    llvm::SDValue& Lo,
    llvm::SDValue& Hi,
    llvm::EVT HiLoVT,
    llvm::SelectionDAG& DAG,
    llvm::TargetLoweringBase::MulExpansionKind
        Kind,
    llvm::SDValue LL = llvm::SDValue(),
    llvm::SDValue LH = llvm::SDValue(),
    llvm::SDValue RL = llvm::SDValue(),
    llvm::SDValue RH = llvm::SDValue()) const

Description

Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4072

Parameters

llvm::SDNode* N
llvm::SDValue& Lo
llvm::SDValue& Hi
llvm::EVT HiLoVT: The value type to use for the Lo and Hi nodes.
llvm::SelectionDAG& DAG
llvm::TargetLoweringBase::MulExpansionKind Kind
llvm::SDValue LL = llvm::SDValue(): Low bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
llvm::SDValue LH = llvm::SDValue(): High bits of the LHS of the MUL. See LL for meaning.
llvm::SDValue RL = llvm::SDValue(): Low bits of the RHS of the MUL. See LL for meaning
llvm::SDValue RH = llvm::SDValue(): High bits of the RHS of the MUL. See LL for meaning.

Returns

true if the node has been expanded. false if it has not

¶bool expandMULO(llvm::SDNode* Node,
                llvm::SDValue& Result,
                llvm::SDValue& Overflow,
                llvm::SelectionDAG& DAG) const

Description

Method for building the DAG expansion of ISD::[US]MULO. Returns whether expansion was successful and populates the Result and Overflow arguments.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4209

Parameters

llvm::SDNode* Node
llvm::SDValue& Result
llvm::SDValue& Overflow
llvm::SelectionDAG& DAG

¶bool expandMUL_LOHI(
    unsigned int Opcode,
    llvm::EVT VT,
    llvm::SDLoc dl,
    llvm::SDValue LHS,
    llvm::SDValue RHS,
    SmallVectorImpl<llvm::SDValue>& Result,
    llvm::EVT HiLoVT,
    llvm::SelectionDAG& DAG,
    llvm::TargetLoweringBase::MulExpansionKind
        Kind,
    llvm::SDValue LL = llvm::SDValue(),
    llvm::SDValue LH = llvm::SDValue(),
    llvm::SDValue RL = llvm::SDValue(),
    llvm::SDValue RH = llvm::SDValue()) const

Description

Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4057

Parameters

unsigned int Opcode
llvm::EVT VT
llvm::SDLoc dl
llvm::SDValue LHS
llvm::SDValue RHS
SmallVectorImpl<llvm::SDValue>& Result: A vector that will be filled with the parts of the result in little-endian order.
llvm::EVT HiLoVT
llvm::SelectionDAG& DAG
llvm::TargetLoweringBase::MulExpansionKind Kind
llvm::SDValue LL = llvm::SDValue(): Low bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
llvm::SDValue LH = llvm::SDValue(): High bits of the LHS of the MUL. See LL for meaning.
llvm::SDValue RL = llvm::SDValue(): Low bits of the RHS of the MUL. See LL for meaning
llvm::SDValue RH = llvm::SDValue(): High bits of the RHS of the MUL. See LL for meaning.

Returns

true if the node has been expanded, false if it has not

¶bool expandROT(llvm::SDNode* N,
               llvm::SDValue& Result,
               llvm::SelectionDAG& DAG) const

Description

Expand rotations.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4087

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶void expandSADDSUBO(llvm::SDNode* Node,
                    llvm::SDValue& Result,
                    llvm::SDValue& Overflow,
                    llvm::SelectionDAG& DAG) const

Description

Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion always suceeds and populates the Result and Overflow arguments.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4204

Parameters

llvm::SDNode* Node
llvm::SDValue& Result
llvm::SDValue& Overflow
llvm::SelectionDAG& DAG

¶void expandUADDSUBO(llvm::SDNode* Node,
                    llvm::SDValue& Result,
                    llvm::SDValue& Overflow,
                    llvm::SelectionDAG& DAG) const

Description

Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion always suceeds and populates the Result and Overflow arguments.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4199

Parameters

llvm::SDNode* Node
llvm::SDValue& Result
llvm::SDValue& Overflow
llvm::SelectionDAG& DAG

¶bool expandUINT_TO_FP(
    llvm::SDNode* N,
    llvm::SDValue& Result,
    llvm::SDValue& Chain,
    llvm::SelectionDAG& DAG) const

Description

Expand UINT(i64) to double(f64) conversion

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4108

Parameters

llvm::SDNode* N: Node to expand
llvm::SDValue& Result: output after conversion
llvm::SDValue& Chain: output chain after conversion
llvm::SelectionDAG& DAG

Returns

True, if the expansion was successful, false otherwise

¶std::pair<SDValue, SDValue> expandUnalignedLoad(
    llvm::LoadSDNode* LD,
    llvm::SelectionDAG& DAG) const

Description

Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4156

Parameters

llvm::LoadSDNode* LD
llvm::SelectionDAG& DAG

¶llvm::SDValue expandUnalignedStore(
    llvm::StoreSDNode* ST,
    llvm::SelectionDAG& DAG) const

Description

Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4161

Parameters

llvm::StoreSDNode* ST
llvm::SelectionDAG& DAG

¶llvm::SDValue expandVecReduce(
    llvm::SDNode* Node,
    llvm::SelectionDAG& DAG) const

Description

Expand a VECREDUCE_* into an explicit calculation. If Count is specified, only the first Count elements of the vector are used.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4214

Parameters

llvm::SDNode* Node
llvm::SelectionDAG& DAG

¶bool findOptimalMemOpLowering(
    int& MemOps,
    unsigned int Limit,
    uint64_t Size,
    unsigned int DstAlign,
    unsigned int SrcAlign,
    bool IsMemset,
    bool ZeroMemset,
    bool MemcpyStrSrc,
    bool AllowOverlap,
    unsigned int DstAS,
    unsigned int SrcAS,
    const llvm::AttributeList& FuncAttributes)
    const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3091

Parameters

int& MemOps
unsigned int Limit
uint64_t Size
unsigned int DstAlign
unsigned int SrcAlign
bool IsMemset
bool ZeroMemset
bool MemcpyStrSrc
bool AllowOverlap
unsigned int DstAS
unsigned int SrcAS
const llvm::AttributeList& FuncAttributes

¶virtual bool
functionArgumentNeedsConsecutiveRegisters(
    llvm::Type* Ty,
    CallingConv::ID CallConv,
    bool isVarArg) const

Description

For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3734

Parameters

llvm::Type* Ty
CallingConv::ID CallConv
bool isVarArg

¶virtual const char* getClearCacheBuiltinName()
    const

Description

Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cache library call

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3706

¶virtual llvm::TargetLowering::ConstraintType
getConstraintType(
    llvm::StringRef Constraint) const

Description

Given a constraint, return the type of constraint it is for this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3942

Parameters

llvm::StringRef Constraint

¶virtual unsigned int getInlineAsmMemConstraint(
    llvm::StringRef ConstraintCode) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3957

Parameters

llvm::StringRef ConstraintCode

¶virtual unsigned int getJumpTableEncoding() const

Description

Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3006

¶virtual MachineMemOperand::Flags getMMOFlags(
    const llvm::Instruction& I) const

Description

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them. The default implementation does nothing.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3769

Parameters

const llvm::Instruction& I

¶virtual llvm::TargetLowering::ConstraintWeight
getMultipleConstraintMatchWeight(
    llvm::TargetLowering::AsmOperandInfo& info,
    int maIndex) const

Description

Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3925

Parameters

llvm::TargetLowering::AsmOperandInfo& info
int maIndex

¶virtual llvm::SDValue getNegatedExpression(
    llvm::SDValue Op,
    llvm::SelectionDAG& DAG,
    bool LegalOperations,
    bool ForCodeSize,
    unsigned int Depth = 0) const

Description

If isNegatibleForFree returns true, return the newly negated expression.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3424

Parameters

llvm::SDValue Op
llvm::SelectionDAG& DAG
bool LegalOperations
bool ForCodeSize
unsigned int Depth = 0

¶virtual llvm::SDValue getPICJumpTableRelocBase(
    llvm::SDValue Table,
    llvm::SelectionDAG& DAG) const

Description

Returns relocation base for the given PIC jumptable.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3016

Parameters

llvm::SDValue Table
llvm::SelectionDAG& DAG

¶virtual const llvm::MCExpr*
getPICJumpTableRelocBaseExpr(
    const llvm::MachineFunction* MF,
    unsigned int JTI,
    llvm::MCContext& Ctx) const

Description

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3022

Parameters

const llvm::MachineFunction* MF
unsigned int JTI
llvm::MCContext& Ctx

¶virtual bool getPostIndexedAddressParts(
    llvm::SDNode*,
    llvm::SDNode*,
    llvm::SDValue&,
    llvm::SDValue&,
    ISD::MemIndexedMode&,
    llvm::SelectionDAG&) const

Description

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2988

Parameters

llvm::SDNode*
llvm::SDNode*
llvm::SDValue&
llvm::SDValue&
ISD::MemIndexedMode&
llvm::SelectionDAG&

¶virtual bool getPreIndexedAddressParts(
    llvm::SDNode*,
    llvm::SDValue&,
    llvm::SDValue&,
    ISD::MemIndexedMode&,
    llvm::SelectionDAG&) const

Description

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2978

Parameters

llvm::SDNode*
llvm::SDValue&
llvm::SDValue&
ISD::MemIndexedMode&
llvm::SelectionDAG&

¶virtual llvm::SDValue getRecipEstimate(
    llvm::SDValue Operand,
    llvm::SelectionDAG& DAG,
    int Enabled,
    int& RefinementSteps) const

Description

Return a reciprocal estimate value for the input operand.\p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4038

Parameters

llvm::SDValue Operand
llvm::SelectionDAG& DAG
int Enabled
int& RefinementSteps

¶virtual std::pair<unsigned int,
                  const TargetRegisterClass*>
getRegForInlineAsmConstraint(
    const llvm::TargetRegisterInfo* TRI,
    llvm::StringRef Constraint,
    llvm::MVT VT) const

Description

Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer. This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3954

Parameters

const llvm::TargetRegisterInfo* TRI
llvm::StringRef Constraint
llvm::MVT VT

¶virtual llvm::Register getRegisterByName(
    const char* RegName,
    llvm::LLT Ty,
    const llvm::MachineFunction& MF) const

Description

Return the register ID of the name passed in. Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3713

Parameters

const char* RegName
llvm::LLT Ty
const llvm::MachineFunction& MF

¶virtual const llvm::MCPhysReg*
getScratchRegisters(CallingConv::ID CC) const

Description

Returns a 0 terminated array of registers that can be safely used as scratch registers.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3750

Parameters

CallingConv::ID CC

¶virtual llvm::TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(
    llvm::TargetLowering::AsmOperandInfo& info,
    const char* constraint) const

Description

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3930

Parameters

llvm::TargetLowering::AsmOperandInfo& info
const char* constraint

¶virtual llvm::SDValue getSqrtEstimate(
    llvm::SDValue Operand,
    llvm::SelectionDAG& DAG,
    int Enabled,
    int& RefinementSteps,
    bool& UseOneConstNR,
    bool Reciprocal) const

Description

Return either a square root or its reciprocal estimate value for the input operand.\p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. The boolean UseOneConstNR output is used to select a Newton-Raphson algorithm implementation that uses either one or two constants. The boolean Reciprocal is used to select whether the estimate is for the square root of the input operand or the reciprocal of its square root. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4022

Parameters

llvm::SDValue Operand
llvm::SelectionDAG& DAG
int Enabled
int& RefinementSteps
bool& UseOneConstNR
bool Reciprocal

¶virtual const llvm::Constant*
getTargetConstantFromLoad(
    llvm::LoadSDNode* LD) const

Description

This method returns the constant pool value that will be loaded by LD. NOTE: You must check for implicit extensions of the constant by LD.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3260

Parameters

llvm::LoadSDNode* LD

¶virtual const char* getTargetNodeName(
    unsigned int Opcode) const

Description

This method returns the name of a target specific DAG node.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3832

Parameters

unsigned int Opcode

¶virtual llvm::EVT getTypeForExtReturn(
    llvm::LLVMContext& Context,
    llvm::EVT VT,
    ISD::NodeType) const

Description

Return the type that should be used to zero or sign extend a zeroext/signext integer return value. FIXME: Some C calling conventions require the return type to be promoted, but this is not true all the time, e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3724

Parameters

llvm::LLVMContext& Context
llvm::EVT VT
ISD::NodeType

¶llvm::SDValue getVectorElementPointer(
    llvm::SelectionDAG& DAG,
    llvm::SDValue VecPtr,
    llvm::EVT VecVT,
    llvm::SDValue Index) const

Description

Get a pointer to vector element \p Idx located in memory for a vector of type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of bounds the returned pointer is unspecified, but will be within the vector bounds.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4178

Parameters

llvm::SelectionDAG& DAG
llvm::SDValue VecPtr
llvm::EVT VecVT
llvm::SDValue Index

¶virtual void initializeSplitCSR(
    llvm::MachineBasicBlock* Entry) const

Description

Perform necessary initialization to handle a subset of CSRs explicitly via copies. This function is called at the beginning of instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3402

Parameters

llvm::MachineBasicBlock* Entry

¶virtual void insertCopiesSplitCSR(
    llvm::MachineBasicBlock* Entry,
    const SmallVectorImpl<
        llvm::MachineBasicBlock*>& Exits) const

Description

Insert explicit copies in entry and exit blocks. We copy a subset of CSRs to virtual registers in the entry block, and copy them back to physical registers in the exit blocks. This function is called at the end of instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3410

Parameters

llvm::MachineBasicBlock* Entry
const SmallVectorImpl<llvm::MachineBasicBlock*>& Exits

¶bool isConstFalseVal(const llvm::SDNode* N) const

Description

Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3302

Parameters

const llvm::SDNode* N

¶bool isConstTrueVal(const llvm::SDNode* N) const

Description

Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3298

Parameters

const llvm::SDNode* N

¶virtual bool
isDesirableToCombineBuildVectorToShuffleTruncate(
    ArrayRef<int> ShuffleMask,
    llvm::EVT SrcVT,
    llvm::EVT TruncVT) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3358

Parameters

ArrayRef<int> ShuffleMask
llvm::EVT SrcVT
llvm::EVT TruncVT

¶virtual bool isDesirableToCommuteWithShift(
    const llvm::SDNode* N,
    llvm::CombineLevel Level) const

Description

Return true if it is profitable to move this shift by a constant amount though its operand, adjusting any immediate operands as necessary to preserve semantics. This transformation may not be desirable if it disrupts a particularly auspicious target-specific tree (e.g. bitfield extraction in AArch64). By default, it returns true.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3344

Parameters

const llvm::SDNode* N: the shift node
llvm::CombineLevel Level: the current DAGCombine legalization level.

¶virtual bool isDesirableToTransformToIntegerOp(
    unsigned int,
    llvm::EVT) const

Description

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3375

Parameters

unsigned int
llvm::EVT

¶bool isExtendedTrueVal(
    const llvm::ConstantSDNode* N,
    llvm::EVT VT,
    bool SExt) const

Description

Return if \p N is a True value when extended to \p VT.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3305

Parameters

const llvm::ConstantSDNode* N
llvm::EVT VT
bool SExt

¶virtual bool isGAPlusOffset(
    llvm::SDNode* N,
    const llvm::GlobalValue*& GA,
    int64_t& Offset) const

Description

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3319

Parameters

llvm::SDNode* N
const llvm::GlobalValue*& GA
int64_t& Offset

¶bool isInTailCallPosition(
    llvm::SelectionDAG& DAG,
    llvm::SDNode* Node,
    llvm::SDValue& Chain) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3029

Parameters

llvm::SelectionDAG& DAG
llvm::SDNode* Node
llvm::SDValue& Chain

¶virtual bool isIndexingLegal(
    llvm::MachineInstr& MI,
    llvm::Register Base,
    llvm::Register Offset,
    bool IsPre,
    llvm::MachineRegisterInfo& MRI) const

Description

Returns true if the specified base+offset is a legal indexed addressing mode for this target. \p MI is the load or store instruction that is being considered for transformation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2999

Parameters

llvm::MachineInstr& MI
llvm::Register Base
llvm::Register Offset
bool IsPre
llvm::MachineRegisterInfo& MRI

¶virtual bool isKnownNeverNaNForTargetNode(
    llvm::SDValue Op,
    const llvm::SelectionDAG& DAG,
    bool SNaN = false,
    unsigned int Depth = 0) const

Description

If \p SNaN is false,

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3265

Parameters

llvm::SDValue Op
const llvm::SelectionDAG& DAG
bool SNaN = false
unsigned int Depth = 0

Returns

true if \p Op is known to never be any NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling NaN.

¶virtual char isNegatibleForFree(
    llvm::SDValue Op,
    llvm::SelectionDAG& DAG,
    bool LegalOperations,
    bool ForCodeSize,
    unsigned int Depth = 0) const

Description

Return 1 if we can compute the negated form of the specified expression for the same cost as the expression itself, or 2 if we can compute the negated form more cheaply than the expression itself. Else return 0.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3419

Parameters

llvm::SDValue Op
llvm::SelectionDAG& DAG
bool LegalOperations
bool ForCodeSize
unsigned int Depth = 0

¶virtual bool isOffsetFoldingLegal(
    const llvm::GlobalAddressSDNode* GA) const

Description

Return true if folding a constant offset with the given GlobalAddress is legal. It is frequently not legal in PIC relocation models.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3027

Parameters

const llvm::GlobalAddressSDNode* GA

¶bool isPositionIndependent() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2963

¶virtual bool isSDNodeAlwaysUniform(
    const llvm::SDNode* N) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2971

Parameters

const llvm::SDNode* N

¶virtual bool isSDNodeSourceOfDivergence(
    const llvm::SDNode* N,
    llvm::FunctionLoweringInfo* FLI,
    llvm::LegacyDivergenceAnalysis* DA) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2965

Parameters

const llvm::SDNode* N
llvm::FunctionLoweringInfo* FLI
llvm::LegacyDivergenceAnalysis* DA

¶virtual bool isTypeDesirableForOp(
    unsigned int,
    llvm::EVT VT) const

Description

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3367

Parameters

unsigned int
llvm::EVT VT

¶virtual bool isUsedByReturnOnly(
    llvm::SDNode*,
    llvm::SDValue&) const

Description

Return true if result of the specified node is used by a return node only. It also compute and return the input chain for the tail call. This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3693

Parameters

llvm::SDNode*
llvm::SDValue&

¶virtual bool lowerAtomicLoadAsLoadSDNode(
    const llvm::LoadInst& LI) const

Description

Should SelectionDAG lower an atomic load of the given kind as a normal LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to eventually migrate all targets to the using LoadSDNodes, but porting is being done target at a time.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3786

Parameters

const llvm::LoadInst& LI

¶virtual bool lowerAtomicStoreAsStoreSDNode(
    const llvm::StoreInst& SI) const

Description

Should SelectionDAG lower an atomic store of the given kind as a normal StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to eventually migrate all targets to the using StoreSDNodes, but porting is being done target at a time.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3777

Parameters

const llvm::StoreInst& SI

¶llvm::SDValue lowerCmpEqZeroToCtlzSrl(
    llvm::SDValue Op,
    llvm::SelectionDAG& DAG) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4264

Parameters

llvm::SDValue Op
llvm::SelectionDAG& DAG

¶std::pair<SDValue, SDValue> makeLibCall(
    llvm::SelectionDAG& DAG,
    RTLIB::Libcall LC,
    llvm::EVT RetVT,
    ArrayRef<llvm::SDValue> Ops,
    llvm::TargetLowering::MakeLibCallOptions
        CallOptions,
    const llvm::SDLoc& dl,
    llvm::SDValue Chain = llvm::SDValue()) const

Description

Returns a pair of (return value, chain). It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3045

Parameters

llvm::SelectionDAG& DAG
RTLIB::Libcall LC
llvm::EVT RetVT
ArrayRef<llvm::SDValue> Ops
llvm::TargetLowering::MakeLibCallOptions CallOptions
const llvm::SDLoc& dl
llvm::SDValue Chain = llvm::SDValue()

¶virtual bool mayBeEmittedAsTailCall(
    const llvm::CallInst*) const

Description

Return true if the target may be able emit the call instruction as a tail call. This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3700

Parameters

const llvm::CallInst*

¶bool parametersInCSRMatch(
    const llvm::MachineRegisterInfo& MRI,
    const uint32_t* CallerPreservedMask,
    const SmallVectorImpl<llvm::CCValAssign>&
        ArgLocs,
    const SmallVectorImpl<llvm::SDValue>& OutVals)
    const

Description

Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function. This needs to be checked for tail call eligibility.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3054

Parameters

const llvm::MachineRegisterInfo& MRI
const uint32_t* CallerPreservedMask
const SmallVectorImpl<llvm::CCValAssign>& ArgLocs
const SmallVectorImpl<llvm::SDValue>& OutVals

¶virtual llvm::SDValue prepareVolatileOrAtomicLoad(
    llvm::SDValue Chain,
    const llvm::SDLoc& DL,
    llvm::SelectionDAG& DAG) const

Description

This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself. Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3761

Parameters

llvm::SDValue Chain
const llvm::SDLoc& DL
llvm::SelectionDAG& DAG

¶std::pair<SDValue, SDValue> scalarizeVectorLoad(
    llvm::LoadSDNode* LD,
    llvm::SelectionDAG& DAG) const

Description

Turn load of vector type into a load of the individual elements.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4146

Parameters

llvm::LoadSDNode* LD: load to expand
llvm::SelectionDAG& DAG

Returns

BUILD_VECTOR and TokenFactor nodes.

¶llvm::SDValue scalarizeVectorStore(
    llvm::StoreSDNode* ST,
    llvm::SelectionDAG& DAG) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4152

Parameters

llvm::StoreSDNode* ST: Store with a vector value type
llvm::SelectionDAG& DAG

Returns

TokenFactor of the individual store chains.

¶virtual bool
shouldSplitFunctionArgumentsAsLittleEndian(
    const llvm::DataLayout& DL) const

Description

For most targets, an LLVM type must be broken down into multiple smaller types. Usually the halves are ordered according to the endianness but for some platform that would break. So this method will default to matching the endianness but can be overridden.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3744

Parameters

const llvm::DataLayout& DL

¶void softenSetCCOperands(
    llvm::SelectionDAG& DAG,
    llvm::EVT VT,
    llvm::SDValue& NewLHS,
    llvm::SDValue& NewRHS,
    ISD::CondCode& CCCode,
    const llvm::SDLoc& DL,
    const llvm::SDValue OldLHS,
    const llvm::SDValue OldRHS,
    llvm::SDValue& Chain,
    bool IsSignaling = false) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3037

Parameters

llvm::SelectionDAG& DAG
llvm::EVT VT
llvm::SDValue& NewLHS
llvm::SDValue& NewRHS
ISD::CondCode& CCCode
const llvm::SDLoc& DL
const llvm::SDValue OldLHS
const llvm::SDValue OldRHS
llvm::SDValue& Chain
bool IsSignaling = false

¶void softenSetCCOperands(
    llvm::SelectionDAG& DAG,
    llvm::EVT VT,
    llvm::SDValue& NewLHS,
    llvm::SDValue& NewRHS,
    ISD::CondCode& CCCode,
    const llvm::SDLoc& DL,
    const llvm::SDValue OldLHS,
    const llvm::SDValue OldRHS) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3032

Parameters

llvm::SelectionDAG& DAG
llvm::EVT VT
llvm::SDValue& NewLHS
llvm::SDValue& NewRHS
ISD::CondCode& CCCode
const llvm::SDLoc& DL
const llvm::SDValue OldLHS
const llvm::SDValue OldRHS

¶virtual bool supportSplitCSR(
    llvm::MachineFunction* MF) const

Description

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3395

Parameters

llvm::MachineFunction* MF

¶virtual bool supportSwiftError() const

Description

Return true if the target supports swifterror attribute. It optimizes loads and stores to reading and writing a specific register.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3389

¶virtual bool targetShrinkDemandedConstant(
    llvm::SDValue Op,
    const llvm::APInt& Demanded,
    llvm::TargetLowering::TargetLoweringOpt& TLO)
    const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3111

Parameters

llvm::SDValue Op
const llvm::APInt& Demanded
llvm::TargetLowering::TargetLoweringOpt& TLO

¶virtual llvm::SDValue unwrapAddress(
    llvm::SDValue N) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3314

Parameters

llvm::SDValue N

¶virtual bool useLoadStackGuardNode() const

Description

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:4240

¶bool verifyReturnAddressArgumentIsConstant(
    llvm::SDValue Op,
    llvm::SelectionDAG& DAG) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:3841

Parameters

llvm::SDValue Op
llvm::SelectionDAG& DAG

class TargetLowering

Declaration

Member Variables

Method Overview

Methods

¶virtual void AdjustInstrPostInstrSelection( llvm::MachineInstr& MI, llvm::SDNode* Node) const

Description

Parameters

¶llvm::SDValue BuildSDIV( llvm::SDNode* N, llvm::SelectionDAG& DAG, bool IsAfterLegalization, SmallVectorImpl<llvm::SDNode*>& Created) const

Parameters

¶virtual llvm::SDValue BuildSDIVPow2( llvm::SDNode* N, const llvm::APInt& Divisor, llvm::SelectionDAG& DAG, SmallVectorImpl<llvm::SDNode*>& Created) const

Description

Parameters

¶llvm::SDValue BuildUDIV( llvm::SDNode* N, llvm::SelectionDAG& DAG, bool IsAfterLegalization, SmallVectorImpl<llvm::SDNode*>& Created) const

Parameters

¶virtual bool CanLowerReturn( CallingConv::ID, llvm::MachineFunction&, bool, const SmallVectorImpl<ISD::OutputArg>&, llvm::LLVMContext&) const

Description

Parameters

¶virtual void ComputeConstraintToUse( llvm::TargetLowering::AsmOperandInfo& OpInfo, llvm::SDValue Op, llvm::SelectionDAG* DAG = nullptr) const

Description

Parameters

¶virtual unsigned int ComputeNumSignBitsForTargetNode( llvm::SDValue Op, const llvm::APInt& DemandedElts, const llvm::SelectionDAG& DAG, unsigned int Depth = 0) const

Description

Parameters

¶virtual llvm::MachineBasicBlock* EmitInstrWithCustomInserter( llvm::MachineInstr& MI, llvm::MachineBasicBlock* MBB) const

Description

Parameters

¶virtual bool ExpandInlineAsm( llvm::CallInst*) const

Description

Parameters

¶virtual void HandleByVal(llvm::CCState*, unsigned int&, unsigned int) const

Description

Parameters

¶llvm::SDValue IncrementMemoryAddress( llvm::SDValue Addr, llvm::SDValue Mask, const llvm::SDLoc& DL, llvm::EVT DataVT, llvm::SelectionDAG& DAG, bool IsCompressedMemory) const

Description

Parameters

¶virtual bool IsDesirableToPromoteOp( llvm::SDValue, llvm::EVT&) const

Description

Parameters

¶virtual void LowerAsmOperandForConstraint( llvm::SDValue Op, std::string& Constraint, int& Ops, llvm::SelectionDAG& DAG) const

Parameters

¶virtual llvm::SDValue LowerAsmOutputForConstraint( llvm::SDValue& Chain, llvm::SDValue& Flag, llvm::SDLoc DL, const llvm::TargetLowering::AsmOperandInfo& OpInfo, llvm::SelectionDAG& DAG) const

Parameters

¶virtual llvm::SDValue LowerCall( llvm::TargetLowering::CallLoweringInfo&, SmallVectorImpl<llvm::SDValue>&) const

Description

Parameters

¶std::pair<SDValue, SDValue> LowerCallTo( llvm::TargetLowering::CallLoweringInfo& CLI) const

Description

Parameters

¶virtual const llvm::MCExpr* LowerCustomJumpTableEntry( const llvm::MachineJumpTableInfo*, const llvm::MachineBasicBlock*, unsigned int, llvm::MCContext&) const

Parameters

¶virtual llvm::SDValue LowerFormalArguments( llvm::SDValue, CallingConv::ID, bool, const SmallVectorImpl<ISD::InputArg>&, const llvm::SDLoc&, llvm::SelectionDAG&, SmallVectorImpl<llvm::SDValue>&) const

Description

Parameters

¶virtual llvm::SDValue LowerOperation( llvm::SDValue Op, llvm::SelectionDAG& DAG) const

Description

Parameters

¶virtual void LowerOperationWrapper( llvm::SDNode* N, SmallVectorImpl<llvm::SDValue>& Results, llvm::SelectionDAG& DAG) const

Description

Parameters

¶virtual llvm::SDValue LowerReturn( llvm::SDValue, CallingConv::ID, bool, const SmallVectorImpl<ISD::OutputArg>&, const SmallVectorImpl<llvm::SDValue>&, const llvm::SDLoc&, llvm::SelectionDAG&) const

Description

Parameters

¶virtual llvm::SDValue LowerToTLSEmulatedModel( const llvm::GlobalAddressSDNode* GA, llvm::SelectionDAG& DAG) const

Description

Parameters

¶virtual const char* LowerXConstraint( llvm::EVT ConstraintVT) const

Description

Parameters

¶int ParseConstraints( const llvm::DataLayout& DL, const llvm::TargetRegisterInfo* TRI, llvm::ImmutableCallSite CS) const

Parameters

¶virtual llvm::SDValue PerformDAGCombine( llvm::SDNode* N, llvm::TargetLowering::DAGCombinerInfo& DCI) const

Description

Parameters

¶virtual void ReplaceNodeResults( llvm::SDNode*, SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const

Description

Parameters

¶bool ShrinkDemandedConstant( llvm::SDValue Op, const llvm::APInt& Demanded, llvm::TargetLowering::TargetLoweringOpt& TLO) const

Description

Parameters

¶`virtual void AdjustInstrPostInstrSelection( llvm::MachineInstr& MI, llvm::SDNode* Node) const`

¶`llvm::SDValue BuildSDIV( llvm::SDNode* N, llvm::SelectionDAG& DAG, bool IsAfterLegalization, SmallVectorImpl<llvm::SDNode*>& Created) const`

¶`virtual llvm::SDValue BuildSDIVPow2( llvm::SDNode* N, const llvm::APInt& Divisor, llvm::SelectionDAG& DAG, SmallVectorImpl<llvm::SDNode*>& Created) const`

¶`llvm::SDValue BuildUDIV( llvm::SDNode* N, llvm::SelectionDAG& DAG, bool IsAfterLegalization, SmallVectorImpl<llvm::SDNode*>& Created) const`

¶`virtual bool CanLowerReturn( CallingConv::ID, llvm::MachineFunction&, bool, const SmallVectorImpl<ISD::OutputArg>&, llvm::LLVMContext&) const`

¶`virtual void ComputeConstraintToUse( llvm::TargetLowering::AsmOperandInfo& OpInfo, llvm::SDValue Op, llvm::SelectionDAG* DAG = nullptr) const`

¶`virtual unsigned int ComputeNumSignBitsForTargetNode( llvm::SDValue Op, const llvm::APInt& DemandedElts, const llvm::SelectionDAG& DAG, unsigned int Depth = 0) const`

¶`virtual llvm::MachineBasicBlock* EmitInstrWithCustomInserter( llvm::MachineInstr& MI, llvm::MachineBasicBlock* MBB) const`

¶`virtual bool ExpandInlineAsm( llvm::CallInst*) const`

¶`virtual void HandleByVal(llvm::CCState*, unsigned int&, unsigned int) const`

¶`llvm::SDValue IncrementMemoryAddress( llvm::SDValue Addr, llvm::SDValue Mask, const llvm::SDLoc& DL, llvm::EVT DataVT, llvm::SelectionDAG& DAG, bool IsCompressedMemory) const`

¶`virtual bool IsDesirableToPromoteOp( llvm::SDValue, llvm::EVT&) const`

¶`virtual void LowerAsmOperandForConstraint( llvm::SDValue Op, std::string& Constraint, int& Ops, llvm::SelectionDAG& DAG) const`

¶`virtual llvm::SDValue LowerAsmOutputForConstraint( llvm::SDValue& Chain, llvm::SDValue& Flag, llvm::SDLoc DL, const llvm::TargetLowering::AsmOperandInfo& OpInfo, llvm::SelectionDAG& DAG) const`

¶`virtual llvm::SDValue LowerCall( llvm::TargetLowering::CallLoweringInfo&, SmallVectorImpl<llvm::SDValue>&) const`

¶`std::pair<SDValue, SDValue> LowerCallTo( llvm::TargetLowering::CallLoweringInfo& CLI) const`

¶`virtual const llvm::MCExpr* LowerCustomJumpTableEntry( const llvm::MachineJumpTableInfo, const llvm::MachineBasicBlock, unsigned int, llvm::MCContext&) const`

¶`virtual llvm::SDValue LowerFormalArguments( llvm::SDValue, CallingConv::ID, bool, const SmallVectorImpl<ISD::InputArg>&, const llvm::SDLoc&, llvm::SelectionDAG&, SmallVectorImpl<llvm::SDValue>&) const`

¶`virtual llvm::SDValue LowerOperation( llvm::SDValue Op, llvm::SelectionDAG& DAG) const`

¶`virtual void LowerOperationWrapper( llvm::SDNode* N, SmallVectorImpl<llvm::SDValue>& Results, llvm::SelectionDAG& DAG) const`

¶`virtual llvm::SDValue LowerReturn( llvm::SDValue, CallingConv::ID, bool, const SmallVectorImpl<ISD::OutputArg>&, const SmallVectorImpl<llvm::SDValue>&, const llvm::SDLoc&, llvm::SelectionDAG&) const`

¶`virtual llvm::SDValue LowerToTLSEmulatedModel( const llvm::GlobalAddressSDNode* GA, llvm::SelectionDAG& DAG) const`

¶`virtual const char* LowerXConstraint( llvm::EVT ConstraintVT) const`

¶`int ParseConstraints( const llvm::DataLayout& DL, const llvm::TargetRegisterInfo* TRI, llvm::ImmutableCallSite CS) const`

¶`virtual llvm::SDValue PerformDAGCombine( llvm::SDNode* N, llvm::TargetLowering::DAGCombinerInfo& DCI) const`

¶`virtual void ReplaceNodeResults( llvm::SDNode*, SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const`

¶`bool ShrinkDemandedConstant( llvm::SDValue Op, const llvm::APInt& Demanded, llvm::TargetLowering::TargetLoweringOpt& TLO) const`

¶`bool ShrinkDemandedOp( llvm::SDValue Op, unsigned int BitWidth, const llvm::APInt& Demanded, llvm::TargetLowering::TargetLoweringOpt& TLO) const`

¶`bool SimplifyDemandedBits( llvm::SDValue Op, const llvm::APInt& DemandedMask, llvm::TargetLowering::DAGCombinerInfo& DCI) const`

¶`bool SimplifyDemandedBits( llvm::SDValue Op, const llvm::APInt& DemandedBits, llvm::KnownBits& Known, llvm::TargetLowering::TargetLoweringOpt& TLO, unsigned int Depth = 0, bool AssumeSingleUse = false) const`

¶`bool SimplifyDemandedBits( llvm::SDValue Op, const llvm::APInt& DemandedBits, const llvm::APInt& DemandedElts, llvm::KnownBits& Known, llvm::TargetLowering::TargetLoweringOpt& TLO, unsigned int Depth = 0, bool AssumeSingleUse = false) const`

¶`virtual bool SimplifyDemandedBitsForTargetNode( llvm::SDValue Op, const llvm::APInt& DemandedBits, const llvm::APInt& DemandedElts, llvm::KnownBits& Known, llvm::TargetLowering::TargetLoweringOpt& TLO, unsigned int Depth = 0) const`

¶`bool SimplifyDemandedVectorElts( llvm::SDValue Op, const llvm::APInt& DemandedEltMask, llvm::APInt& KnownUndef, llvm::APInt& KnownZero, llvm::TargetLowering::TargetLoweringOpt& TLO, unsigned int Depth = 0, bool AssumeSingleUse = false) const`

¶`bool SimplifyDemandedVectorElts( llvm::SDValue Op, const llvm::APInt& DemandedElts, llvm::APInt& KnownUndef, llvm::APInt& KnownZero, llvm::TargetLowering::DAGCombinerInfo& DCI) const`

¶`virtual bool SimplifyDemandedVectorEltsForTargetNode( llvm::SDValue Op, const llvm::APInt& DemandedElts, llvm::APInt& KnownUndef, llvm::APInt& KnownZero, llvm::TargetLowering::TargetLoweringOpt& TLO, unsigned int Depth = 0) const`

¶`llvm::SDValue SimplifyMultipleUseDemandedBits( llvm::SDValue Op, const llvm::APInt& DemandedBits, const llvm::APInt& DemandedElts, llvm::SelectionDAG& DAG, unsigned int Depth) const`

¶`virtual llvm::SDValue SimplifyMultipleUseDemandedBitsForTargetNode( llvm::SDValue Op, const llvm::APInt& DemandedBits, const llvm::APInt& DemandedElts, llvm::SelectionDAG& DAG, unsigned int Depth) const`

¶`llvm::SDValue SimplifySetCC( llvm::EVT VT, llvm::SDValue N0, llvm::SDValue N1, ISD::CondCode Cond, bool foldBooleans, llvm::TargetLowering::DAGCombinerInfo& DCI, const llvm::SDLoc& dl) const`

¶`TargetLowering(const llvm::TargetMachine& TM)`

¶`TargetLowering(const llvm::TargetLowering&)`

¶`llvm::SDValue buildLegalVectorShuffle( llvm::EVT VT, const llvm::SDLoc& DL, llvm::SDValue N0, llvm::SDValue N1, MutableArrayRef<int> Mask, llvm::SelectionDAG& DAG) const`

¶`virtual unsigned int combineRepeatedFPDivisors() const`

¶`virtual void computeKnownBitsForFrameIndex( const llvm::SDValue FIOp, llvm::KnownBits& Known, const llvm::APInt& DemandedElts, const llvm::SelectionDAG& DAG, unsigned int Depth = 0) const`

¶`virtual void computeKnownBitsForTargetInstr( llvm::GISelKnownBits& Analysis, llvm::Register R, llvm::KnownBits& Known, const llvm::APInt& DemandedElts, const llvm::MachineRegisterInfo& MRI, unsigned int Depth = 0) const`

¶`virtual void computeKnownBitsForTargetNode( const llvm::SDValue Op, llvm::KnownBits& Known, const llvm::APInt& DemandedElts, const llvm::SelectionDAG& DAG, unsigned int Depth = 0) const`

¶`virtual llvm::FastISel* createFastISel( llvm::FunctionLoweringInfo&, const llvm::TargetLibraryInfo*) const`

¶`virtual llvm::SDValue emitStackGuardXorFP( llvm::SelectionDAG& DAG, llvm::SDValue Val, const llvm::SDLoc& DL) const`

¶`bool expandABS(llvm::SDNode* N, llvm::SDValue& Result, llvm::SelectionDAG& DAG) const`

¶`llvm::SDValue expandAddSubSat( llvm::SDNode* Node, llvm::SelectionDAG& DAG) const`

¶`bool expandCTLZ(llvm::SDNode* N, llvm::SDValue& Result, llvm::SelectionDAG& DAG) const`

¶`bool expandCTPOP(llvm::SDNode* N, llvm::SDValue& Result, llvm::SelectionDAG& DAG) const`