class MachineInstr

Declaration

class MachineInstr { /* full declaration omitted */ };

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:63

Method Overview

Methods

MachineInstr(const llvm::MachineInstr&)

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:266

Parameters

const llvm::MachineInstr& 

void RemoveOperand(unsigned int OpNo)

Description

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1570

Parameters

unsigned int OpNo

void addImplicitDefUseOperands(
    llvm::MachineFunction& MF)

Description

Add all implicit def and use operands to this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1652

Parameters

llvm::MachineFunction& MF

void addMemOperand(llvm::MachineFunction& MF,
                   llvm::MachineMemOperand* MO)

Description

Add a MachineMemOperand to the machine instruction. This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1587

Parameters

llvm::MachineFunction& MF
llvm::MachineMemOperand* MO

void addOperand(llvm::MachineFunction& MF,
                const llvm::MachineOperand& Op)

Description

Add the specified operand to the instruction. If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand). MF must be the machine function that was used to allocate this instruction. MachineInstrBuilder provides a more convenient interface for creating instructions and adding operands.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1548

Parameters

llvm::MachineFunction& MF
const llvm::MachineOperand& Op

void addOperand(const llvm::MachineOperand& Op)

Description

Add an operand without providing an MF reference. This only works for instructions that are inserted in a basic block. MachineInstrBuilder and the two-argument addOperand(MF, MO) should be preferred.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1555

Parameters

const llvm::MachineOperand& Op

bool addRegisterDead(
    llvm::Register Reg,
    const llvm::TargetRegisterInfo* RegInfo,
    bool AddIfNotFound = false)

Description

We have determined MI defined a register without a use. Look for the operand that defines it and mark it as IsDead. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1413

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* RegInfo
bool AddIfNotFound = false

void addRegisterDefined(
    llvm::Register Reg,
    const llvm::TargetRegisterInfo* RegInfo =
        nullptr)

Description

We have determined MI defines a register. Make sure there is an operand defining Reg.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1426

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* RegInfo = nullptr

bool addRegisterKilled(
    llvm::Register IncomingReg,
    const llvm::TargetRegisterInfo* RegInfo,
    bool AddIfNotFound = false)

Description

We have determined MI kills a register. Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1401

Parameters

llvm::Register IncomingReg
const llvm::TargetRegisterInfo* RegInfo
bool AddIfNotFound = false

bool allDefsAreDead() const

Description

Return true if all the defs of this instruction are dead.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1486

void bundleWithPred()

Description

Bundle this instruction with its predecessor. This can be an unbundled instruction, or it can be the first instruction in a bundle.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:387

void bundleWithSucc()

Description

Bundle this instruction with its successor. This can be an unbundled instruction, or it can be the last instruction in a bundle.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:391

bool canFoldAsLoad(llvm::MachineInstr::QueryType
                       Type = IgnoreBundle) const

Description

Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:802

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

void changeDebugValuesDefReg(llvm::Register Reg)

Description

Find all DBG_VALUEs that point to the register def in this instruction and point them to \p Reg instead.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1660

Parameters

llvm::Register Reg

void clearAsmPrinterFlag(
    llvm::MachineInstr::CommentFlag Flag)

Description

Clear specific AsmPrinter flags.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:302

Parameters

llvm::MachineInstr::CommentFlag Flag

void clearAsmPrinterFlags()

Description

Clear the AsmPrinter bitvector.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:289

void clearFlag(llvm::MachineInstr::MIFlag Flag)

Description

clearFlag - Clear a MI flag.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:328

Parameters

llvm::MachineInstr::MIFlag Flag

void clearKillInfo()

Description

Clears kill flags on all operands.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1390

void clearRegisterDeads(llvm::Register Reg)

Description

Clear all dead flags on operands defining register @p Reg.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1417

Parameters

llvm::Register Reg

void clearRegisterKills(
    llvm::Register Reg,
    const llvm::TargetRegisterInfo* RegInfo)

Description

Clear all kill flags affecting Reg. If RegInfo is provided, this includes all aliasing registers.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1407

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* RegInfo

void cloneInstrSymbols(
    llvm::MachineFunction& MF,
    const llvm::MachineInstr& MI)

Description

Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1624

Parameters

llvm::MachineFunction& MF
const llvm::MachineInstr& MI

void cloneMemRefs(llvm::MachineFunction& MF,
                  const llvm::MachineInstr& MI)

Description

Clone another MachineInstr's memory reference descriptor list and replace ours with it. Note that `*this` may be the incoming MI! Prefer this API whenever possible as it can avoid allocations in common cases.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1596

Parameters

llvm::MachineFunction& MF
const llvm::MachineInstr& MI

void cloneMergedMemRefs(
    llvm::MachineFunction& MF,
    ArrayRef<const llvm::MachineInstr*> MIs)

Description

Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it. Note that `*this` may be one of the incoming MIs! Prefer this API whenever possible as it can avoid allocations in common cases.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1605

Parameters

llvm::MachineFunction& MF
ArrayRef<const llvm::MachineInstr*> MIs

void collectDebugValues(
    SmallVectorImpl<llvm::MachineInstr*>&
        DbgValues)

Description

Scan instructions immediately following MI and collect any matching DBG_VALUEs.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1656

Parameters

SmallVectorImpl<llvm::MachineInstr*>& DbgValues

static uint16_t copyFlagsFromInstruction(
    const llvm::Instruction& I)

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1637

Parameters

const llvm::Instruction& I

void copyIRFlags(const llvm::Instruction& I)

Description

Copy all flags to MachineInst MIFlags

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1640

Parameters

const llvm::Instruction& I

void copyImplicitOps(llvm::MachineFunction& MF,
                     const llvm::MachineInstr& MI)

Description

Copy implicit register operands from specified instruction to this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1503

Parameters

llvm::MachineFunction& MF
const llvm::MachineInstr& MI

bool definesRegister(
    llvm::Register Reg,
    const llvm::TargetRegisterInfo* TRI =
        nullptr) const

Description

Return true if the MachineInstr fully defines the specified register. If TargetRegisterInfo is passed, then it also checks if there is a def of a super-register. NOTE: It's ignoring subreg indices on virtual registers.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1218

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* TRI = nullptr

iterator_range<
    llvm::MachineInstr::const_mop_iterator>
defs() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:519

iterator_range<llvm::MachineInstr::mop_iterator>
defs()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:514

void dropMemRefs(llvm::MachineFunction& MF)

Description

Clear this MachineInstr's memory reference descriptor list. This resets the memrefs to their most conservative state. This should be used only as a last resort since it greatly pessimizes our knowledge of the memory access performed by the instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1576

Parameters

llvm::MachineFunction& MF

void dump() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1532

void emitError(llvm::StringRef Msg) const

Description

Emit an error referring to the source location of this instruction. This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier. If this method returns, the caller should try to recover from the error.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:420

Parameters

llvm::StringRef Msg

void eraseFromBundle()

Description

Unlink 'this' form its basic block and delete it. If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1037

void eraseFromParent()

Description

Unlink 'this' from the containing basic block and delete it. If this instruction is the header of a bundle, the whole bundle is erased. This function can not be used for instructions inside a bundle, use eraseFromBundle() to erase individual bundled instructions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1025

void eraseFromParentAndMarkDBGValuesForRemoval()

Description

Unlink 'this' from the containing basic block and delete it. For all definitions mark their uses in DBG_VALUE nodes as undefined. Otherwise like eraseFromParent().

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1031

iterator_range<llvm::MachineInstr::mop_iterator>
explicit_operands()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:498

iterator_range<
    llvm::MachineInstr::const_mop_iterator>
explicit_operands() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:502

iterator_range<
    llvm::MachineInstr::const_mop_iterator>
explicit_uses() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:536

iterator_range<llvm::MachineInstr::mop_iterator>
explicit_uses()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:532

int findFirstPredOperandIdx() const

Description

Find the index of the first operand in the operand list that is used to represent the predicate. It returns -1 if none is found.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1294

int findInlineAsmFlagIdx(
    unsigned int OpIdx,
    unsigned int* GroupNo = nullptr) const

Description

Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. Returns -1 if getOperand(OpIdx) does not belong to an inline asm operand group. If GroupNo is not NULL, it will receive the number of the operand group containing OpIdx. The flag operand is an immediate that can be decoded with methods like InlineAsm::hasRegClassConstraint().

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1305

Parameters

unsigned int OpIdx
unsigned int* GroupNo = nullptr

const llvm::MachineOperand*
findRegisterDefOperand(
    llvm::Register Reg,
    bool isDead = false,
    bool Overlap = false,
    const llvm::TargetRegisterInfo* TRI =
        nullptr) const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1284

Parameters

llvm::Register Reg
bool isDead = false
bool Overlap = false
const llvm::TargetRegisterInfo* TRI = nullptr

llvm::MachineOperand* findRegisterDefOperand(
    llvm::Register Reg,
    bool isDead = false,
    bool Overlap = false,
    const llvm::TargetRegisterInfo* TRI = nullptr)

Description

Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1276

Parameters

llvm::Register Reg
bool isDead = false
bool Overlap = false
const llvm::TargetRegisterInfo* TRI = nullptr

int findRegisterDefOperandIdx(
    llvm::Register Reg,
    bool isDead = false,
    bool Overlap = false,
    const llvm::TargetRegisterInfo* TRI =
        nullptr) const

Description

Returns the operand index that is a def of the specified register or -1 if it is not found. If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. This may also return a register mask operand when Overlap is true.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1269

Parameters

llvm::Register Reg
bool isDead = false
bool Overlap = false
const llvm::TargetRegisterInfo* TRI = nullptr

const llvm::MachineOperand*
findRegisterUseOperand(
    llvm::Register Reg,
    bool isKill = false,
    const llvm::TargetRegisterInfo* TRI =
        nullptr) const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1256

Parameters

llvm::Register Reg
bool isKill = false
const llvm::TargetRegisterInfo* TRI = nullptr

llvm::MachineOperand* findRegisterUseOperand(
    llvm::Register Reg,
    bool isKill = false,
    const llvm::TargetRegisterInfo* TRI = nullptr)

Description

Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1250

Parameters

llvm::Register Reg
bool isKill = false
const llvm::TargetRegisterInfo* TRI = nullptr

int findRegisterUseOperandIdx(
    llvm::Register Reg,
    bool isKill = false,
    const llvm::TargetRegisterInfo* TRI =
        nullptr) const

Description

Returns the operand index that is a use of the specific register or -1 if it is not found. It further tightens the search criteria to a use that kills the register if isKill is true.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1245

Parameters

llvm::Register Reg
bool isKill = false
const llvm::TargetRegisterInfo* TRI = nullptr

unsigned int findTiedOperandIdx(
    unsigned int OpIdx) const

Description

Given the index of a tied register operand, find the operand it is tied to. Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1360

Parameters

unsigned int OpIdx

bool getAsmPrinterFlag(
    llvm::MachineInstr::CommentFlag Flag) const

Description

Return whether an AsmPrinter flag is set.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:292

Parameters

llvm::MachineInstr::CommentFlag Flag

uint8_t getAsmPrinterFlags() const

Description

Return the asm printer flags bitvector.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:286

unsigned int getBundleSize() const

Description

Return the number of instructions inside the MI bundle, excluding the bundle header. This is the number of instructions that MachineBasicBlock::iterator skips, 0 for unbundled instructions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1181

const llvm::DIExpression* getDebugExpression()
    const

Description

Return the complex address expression referenced by this DBG_VALUE instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:408

const llvm::DILabel* getDebugLabel() const

Description

Return the debug label referenced by this DBG_LABEL instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:412

const llvm::DebugLoc& getDebugLoc() const

Description

Returns the debug location id of this MachineInstr.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:400

const llvm::DILocalVariable* getDebugVariable()
    const

Description

Return the debug variable referenced by this DBG_VALUE instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:404

const llvm::MCInstrDesc& getDesc() const

Description

Returns the target instruction descriptor of this MachineInstr.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:423

bool getFlag(
    llvm::MachineInstr::MIFlag Flag) const

Description

Return whether an MI flag is set.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:312

Parameters

llvm::MachineInstr::MIFlag Flag

uint16_t getFlags() const

Description

Return the MI flags bitvector.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:307

Optional<unsigned int> getFoldedRestoreSize(
    const llvm::TargetInstrInfo* TII) const

Description

Return a valid size if the instruction is a folded restore instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1499

Parameters

const llvm::TargetInstrInfo* TII

Optional<unsigned int> getFoldedSpillSize(
    const llvm::TargetInstrInfo* TII) const

Description

Return a valid size if the instruction is a folded spill instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1492

Parameters

const llvm::TargetInstrInfo* TII

llvm::MDNode* getHeapAllocMarker() const

Description

Helper to extract a heap alloc marker if one has been added.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:612

InlineAsm::AsmDialect getInlineAsmDialect() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1097

unsigned int getIntrinsicID() const

Description

Returns the Intrinsic::ID for this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1664

llvm::MachineFunction* getMF()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:280

const llvm::MachineFunction* getMF() const

Description

Return the function that contains the basic block that this instruction belongs to. Note: this is undefined behaviour if the instruction does not have a parent.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:279

unsigned int getNumDefs() const

Description

Returns the total number of definitions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:441

unsigned int getNumExplicitDefs() const

Description

Returns the number of non-implicit definitions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:480

unsigned int getNumExplicitOperands() const

Description

Returns the number of non-implicit operands.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:477

unsigned int getNumImplicitOperands() const

Description

Returns the implicit operands number.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:457

unsigned int getNumMemOperands() const

Description

Return the number of memory operands.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:585

unsigned int getNumOperands() const

Description

Retuns the total number of operands.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:429

unsigned int getOpcode() const

Description

Returns the opcode of this MachineInstr.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:426

llvm::MachineOperand& getOperand(unsigned int i)

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:435

Parameters

unsigned int i

const llvm::MachineOperand& getOperand(
    unsigned int i) const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:431

Parameters

unsigned int i

unsigned int getOperandNo(
    llvm::MachineInstr::const_mop_iterator I)
    const

Description

Returns the number of the operand iterator \p I points to.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:542

Parameters

llvm::MachineInstr::const_mop_iterator I

llvm::MachineBasicBlock* getParent()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:272

const llvm::MachineBasicBlock* getParent() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:271

llvm::MCSymbol* getPostInstrSymbol() const

Description

Helper to extract a post-instruction symbol if one has been added.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:600

llvm::MCSymbol* getPreInstrSymbol() const

Description

Helper to extract a pre-instruction symbol if one has been added.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:588

const llvm::TargetRegisterClass*
getRegClassConstraint(
    unsigned int OpIdx,
    const llvm::TargetInstrInfo* TII,
    const llvm::TargetRegisterInfo* TRI) const

Description

Compute the static register class constraint for operand OpIdx. For normal instructions, this is derived from the MCInstrDesc. For inline assembly it is derived from the flag words. Returns NULL if the static register class constraint cannot be determined.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1314

Parameters

unsigned int OpIdx
const llvm::TargetInstrInfo* TII
const llvm::TargetRegisterInfo* TRI

const llvm::TargetRegisterClass*
getRegClassConstraintEffect(
    unsigned int OpIdx,
    const llvm::TargetRegisterClass* CurRC,
    const llvm::TargetInstrInfo* TII,
    const llvm::TargetRegisterInfo* TRI) const

Description

Applies the constraints (def/use) implied by the \p OpIdx operand to the given \p CurRC. Returns the register class that satisfies both \p CurRC and the constraints set by \p OpIdx MI. Returns NULL if such a register class does not exist.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1345

Parameters

unsigned int OpIdx
const llvm::TargetRegisterClass* CurRC
const llvm::TargetInstrInfo* TII
const llvm::TargetRegisterInfo* TRI

const llvm::TargetRegisterClass*
getRegClassConstraintEffectForVReg(
    llvm::Register Reg,
    const llvm::TargetRegisterClass* CurRC,
    const llvm::TargetInstrInfo* TII,
    const llvm::TargetRegisterInfo* TRI,
    bool ExploreBundle = false) const

Description

Applies the constraints (def/use) implied by this MI on \p Reg to the given \p CurRC. If \p ExploreBundle is set and MI is part of a bundle, all the instructions inside the bundle will be taken into account. In other words, this method accumulates all the constraints of the operand of this MI and the related bundle if MI is a bundle or inside a bundle. Returns the register class that satisfies both \p CurRC and the constraints set by MI. Returns NULL if such a register class does not exist.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1330

Parameters

llvm::Register Reg
const llvm::TargetRegisterClass* CurRC
const llvm::TargetInstrInfo* TII
const llvm::TargetRegisterInfo* TRI
bool ExploreBundle = false

Optional<unsigned int> getRestoreSize(
    const llvm::TargetInstrInfo* TII) const

Description

Return a valid size if the instruction is a restore instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1495

Parameters

const llvm::TargetInstrInfo* TII

Optional<unsigned int> getSpillSize(
    const llvm::TargetInstrInfo* TII) const

Description

Return a valid size if the instruction is a spill instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1489

Parameters

const llvm::TargetInstrInfo* TII

llvm::LLT getTypeToPrint(
    unsigned int OpIdx,
    llvm::SmallBitVector& PrintedTypes,
    const llvm::MachineRegisterInfo& MRI) const

Description

Debugging support @ { Determine the generic type to be printed (if needed) on uses and defs.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1508

Parameters

unsigned int OpIdx
llvm::SmallBitVector& PrintedTypes
const llvm::MachineRegisterInfo& MRI

bool hasComplexRegisterTies() const

Description

Return true when an instruction has tied register that can't be determined by the instruction's descriptor. This is useful for MIR printing, to determine whether we need to print the ties or not.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1514

bool hasDelaySlot(llvm::MachineInstr::QueryType
                      Type = AnyInBundle) const

Description

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:790

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool hasExtraDefRegAllocReq(
    llvm::MachineInstr::QueryType Type =
        AnyInBundle) const

Description

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:987

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool hasExtraSrcRegAllocReq(
    llvm::MachineInstr::QueryType Type =
        AnyInBundle) const

Description

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:977

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool hasImplicitDef() const

Description

Returns true if the instruction has implicit definition.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:446

bool hasOneMemOperand() const

Description

Return true if this instruction has exactly one MachineMemOperand.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:582

bool hasOptionalDef(llvm::MachineInstr::QueryType
                        Type = IgnoreBundle) const

Description

Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:662

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool hasOrderedMemoryRef() const

Description

Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. Return false if it is known to have no ordered or volatile memory references.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1458

bool hasPostISelHook(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this instruction requires *adjustment* after instruction selection by calling a target hook. For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:946

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool hasProperty(unsigned int MCFlag,
                 llvm::MachineInstr::QueryType
                     Type = AnyInBundle) const

Description

Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:635

Parameters

unsigned int MCFlag
llvm::MachineInstr::QueryType Type = AnyInBundle

bool hasRegisterImplicitUseOperand(
    llvm::Register Reg) const

Description

Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers).

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1240

Parameters

llvm::Register Reg

bool hasUnmodeledSideEffects() const

Description

Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. For all instructions, the property is encoded in MCInstrDesc::Flags (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is INLINEASM instruction, in which case the side effect property is encoded in one of its operands (see InlineAsm::Extra_HasSideEffect).

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1480

iterator_range<
    llvm::MachineInstr::const_mop_iterator>
implicit_operands() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:509

iterator_range<llvm::MachineInstr::mop_iterator>
implicit_operands()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:506

bool isAnnotationLabel() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1041

bool isAsCheapAsAMove(
    llvm::MachineInstr::QueryType Type =
        AllInBundle) const

Description

Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:966

Parameters

llvm::MachineInstr::QueryType Type = AllInBundle

bool isBarrier(llvm::MachineInstr::QueryType
                   Type = AnyInBundle) const

Description

Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:689

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isBitcast(llvm::MachineInstr::QueryType
                   Type = IgnoreBundle) const

Description

Return true if this instruction is a bitcast instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:760

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isBranch(llvm::MachineInstr::QueryType Type =
                  AnyInBundle) const

Description

Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:706

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isBundle() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1111

bool isBundled() const

Description

Return true if this instruction part of a bundle. This is true if either itself or its following instruction is marked "InsideBundle".

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:373

bool isBundledWithPred() const

Description

Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:379

bool isBundledWithSucc() const

Description

Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:383

bool isCFIInstruction() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1050

bool isCall(llvm::MachineInstr::QueryType Type =
                AnyInBundle) const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:682

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isCommutable(llvm::MachineInstr::QueryType
                      Type = IgnoreBundle) const

Description

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction. Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:908

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isCompare(llvm::MachineInstr::QueryType
                   Type = IgnoreBundle) const

Description

Return true if this instruction is a comparison.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:743

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isConditionalBranch(
    llvm::MachineInstr::QueryType Type =
        AnyInBundle) const

Description

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:720

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

unsigned int isConstantValuePHI() const

Description

If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1471

bool isConvergent(llvm::MachineInstr::QueryType
                      Type = AnyInBundle) const

Description

Return true if this instruction is convergent. Convergent instructions can not be made control-dependent on any additional values.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:779

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isConvertibleTo3Addr(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size. If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:926

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isCopy() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1115

bool isCopyLike() const

Description

Return true if the instruction behaves like a copy. This does not include native copy instructions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1129

bool isDebugEntryValue() const

Description

A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1071

bool isDebugInstr() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1059

bool isDebugLabel() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1058

bool isDebugValue() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1057

bool isDereferenceableInvariantLoad(
    llvm::AAResults* AA) const

Description

Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function. Examples include loading a value from the constant pool or from the argument area of a function (if it does not change). If the instruction does multiple loads, this returns true only if all of the loads are dereferenceable and invariant.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1467

Parameters

llvm::AAResults* AA

bool isEHLabel() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1039

bool isEHScopeReturn(llvm::MachineInstr::QueryType
                         Type = AnyInBundle) const

Description

Return true if this is an instruction that marks the end of an EH scope, i.e., a catchpad or a cleanuppad instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:678

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isExtractSubreg() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1123

bool isExtractSubregLike(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1 Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:831

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isFullCopy() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1119

bool isGCLabel() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1040

bool isIdenticalTo(
    const llvm::MachineInstr& Other,
    llvm::MachineInstr::MICheckType Check =
        CheckDefs) const

Description

Return true if this instruction is identical to \p Other. Two instructions are identical if they have the same opcode and all their operands are identical (with respect to MachineOperand::isIdenticalTo()). Note that this means liveness related flags (dead, undef, kill) do not affect the notion of identical.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1003

Parameters

const llvm::MachineInstr& Other
llvm::MachineInstr::MICheckType Check = CheckDefs

bool isIdentityCopy() const

Description

Return true is the instruction is an identity copy.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1134

bool isImplicitDef() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1084

bool isIndirectBranch(
    llvm::MachineInstr::QueryType Type =
        AnyInBundle) const

Description

Return true if this is an indirect branch, such as a branch through a register.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:712

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isIndirectDebugValue() const

Description

A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1063

bool isInlineAsm() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1085

bool isInsertSubreg() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1099

bool isInsertSubregLike(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:845

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isInsideBundle() const

Description

Return true if MI is in a bundle (but not the first MI in a bundle). A bundle looks like this before it's finalized: ---------------- | MI | ---------------- | ---------------- | MI * | ---------------- | ---------------- | MI * | ---------------- In this case, the first MI starts a bundle but is not inside a bundle, the next 2 MIs are considered "inside" the bundle. After a bundle is finalized, it looks like this: ---------------- | Bundle | ---------------- | ---------------- | MI * | ---------------- | ---------------- | MI * | ---------------- | ---------------- | MI * | ---------------- The first instruction has the special opcode "BUNDLE". It's not "inside" a bundle, but the next three MIs are.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:367

bool isKill() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1083

bool isLabel() const

Description

Returns true if the MachineInstr represents a label.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1046

bool isLoadFoldBarrier() const

Description

Returns true if it is illegal to fold a load across this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1483

bool isMSInlineAsm() const

Description

FIXME: Seems like a layering violation that the AsmDialect, which is X86 specific, be attached to a generic MachineInstr.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1092

bool isMetaInstruction() const

Description

Return true if this instruction doesn't produce any output in the form of executable instructions.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1141

bool isMoveImmediate(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this instruction is a move immediate (including conditional moves) instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:749

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isMoveReg(llvm::MachineInstr::QueryType
                   Type = IgnoreBundle) const

Description

Return true if this instruction is a register move. (including moving values from subreg to reg)

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:755

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isNotDuplicable(llvm::MachineInstr::QueryType
                         Type = AnyInBundle) const

Description

Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:772

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isOperandSubregIdx(unsigned int OpIdx) const

Description

Return true if operand \p OpIdx is a subregister index.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:462

Parameters

unsigned int OpIdx

bool isPHI() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1079

bool isPosition() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1055

bool isPreISelOpcode(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this is an instruction that should go through the usual legalization steps.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:648

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isPredicable(llvm::MachineInstr::QueryType
                      Type = AllInBundle) const

Description

Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:736

Parameters

llvm::MachineInstr::QueryType Type = AllInBundle

bool isPseudo(llvm::MachineInstr::QueryType Type =
                  IgnoreBundle) const

Description

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:668

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isRegSequence() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1107

bool isRegSequenceLike(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:816

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isRegTiedToDefOperand(
    unsigned int UseOpIdx,
    unsigned int* DefOpIdx = nullptr) const

Description

Return true if the use operand of the specified index is tied to a def operand. It also returns the def operand index by reference if DefOpIdx is not null.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1379

Parameters

unsigned int UseOpIdx
unsigned int* DefOpIdx = nullptr

bool isRegTiedToUseOperand(
    unsigned int DefOpIdx,
    unsigned int* UseOpIdx = nullptr) const

Description

Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints. Returns the first tied use operand index by reference if UseOpIdx is not null.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1366

Parameters

unsigned int DefOpIdx
unsigned int* UseOpIdx = nullptr

bool isRematerializable(
    llvm::MachineInstr::QueryType Type =
        AllInBundle) const

Description

Returns true if this instruction is a candidate for remat. This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematable.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:954

Parameters

llvm::MachineInstr::QueryType Type = AllInBundle

bool isReturn(llvm::MachineInstr::QueryType Type =
                  AnyInBundle) const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:672

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isSafeToMove(llvm::AAResults* AA,
                  bool& SawStore) const

Description

Return true if it is safe to move this instruction. If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1440

Parameters

llvm::AAResults* AA
bool& SawStore

bool isSelect(llvm::MachineInstr::QueryType Type =
                  IgnoreBundle) const

Description

Return true if this instruction is a select instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:765

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool isStackAligningInlineAsm() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1096

bool isSubregToReg() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1103

bool isTerminator(llvm::MachineInstr::QueryType
                      Type = AnyInBundle) const

Description

Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions. Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:698

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isTransient() const

Description

Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1161

bool isUnconditionalBranch(
    llvm::MachineInstr::QueryType Type =
        AnyInBundle) const

Description

Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:728

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool isUndefDebugValue() const

Description

Return true if the instruction is a debug value which describes a part of a variable as unavailable.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1075

bool isVariadic(llvm::MachineInstr::QueryType
                    Type = IgnoreBundle) const

Description

Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:656

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

bool killsRegister(llvm::Register Reg,
                   const llvm::TargetRegisterInfo*
                       TRI = nullptr) const

Description

Return true if the MachineInstr kills the specified register. If TargetRegisterInfo is passed, then it also checks if there is a kill of a super-register.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1209

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* TRI = nullptr

bool mayAlias(llvm::AAResults* AA,
              const llvm::MachineInstr& Other,
              bool UseTBAA) const

Description

Assumes any physical registers used to compute addresses have the same value for both instructions. Returns false if neither instruction writes to memory.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1452

Parameters

llvm::AAResults* AA
Optional alias analysis, used to compare memory operands.
const llvm::MachineInstr& Other
MachineInstr to check aliasing against.
bool UseTBAA
Whether to pass TBAA information to alias analysis.

bool mayLoad(llvm::MachineInstr::QueryType Type =
                 AnyInBundle) const

Description

Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:856

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool mayLoadOrStore(llvm::MachineInstr::QueryType
                        Type = AnyInBundle) const

Description

Return true if this instruction could possibly read or modify memory.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:879

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

bool mayRaiseFPException() const

Description

Return true if this instruction could possibly raise a floating-point exception. This is the case if the instruction is a floating-point instruction that can in principle raise an exception, as indicated by the MCID::MayRaiseFPException property, *and* at the same time, the instruction is used in a context where we expect floating-point exceptions are not disabled, as indicated by the NoFPExcept MI flag.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:889

bool mayStore(llvm::MachineInstr::QueryType Type =
                  AnyInBundle) const

Description

Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:869

Parameters

llvm::MachineInstr::QueryType Type = AnyInBundle

ArrayRef<llvm::MachineMemOperand*> memoperands()
    const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:549

int memoperands_begin() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:567

bool memoperands_empty() const

Description

Return true if we don't have any memory operands which described the memory access done by this instruction. If this is true, calling code must be conservative.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:579

int memoperands_end() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:574

uint16_t mergeFlagsWith(
    const llvm::MachineInstr& Other) const

Description

Return the MIFlags which represent both MachineInstrs. This should be used when merging two MachineInstrs into one. This routine does not modify the MIFlags of this MachineInstr.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1635

Parameters

const llvm::MachineInstr& Other

bool modifiesRegister(
    llvm::Register Reg,
    const llvm::TargetRegisterInfo* TRI) const

Description

Return true if the MachineInstr modifies (fully define or partially define) the specified register. NOTE: It's ignoring subreg indices on virtual registers.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1226

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* TRI

iterator_range<
    llvm::MachineInstr::const_mop_iterator>
operands() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:495

iterator_range<llvm::MachineInstr::mop_iterator>
operands()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:492

llvm::MachineInstr::const_mop_iterator
operands_begin() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:489

llvm::MachineInstr::mop_iterator operands_begin()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:486

llvm::MachineInstr::mop_iterator operands_end()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:487

llvm::MachineInstr::const_mop_iterator
operands_end() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:490

void print(llvm::raw_ostream& OS,
           bool IsStandalone = true,
           bool SkipOpers = false,
           bool SkipDebugLoc = false,
           bool AddNewLine = true,
           const llvm::TargetInstrInfo* TII =
               nullptr) const

Description

Print this MI to \p OS. Don't print information that can be inferred from other instructions if\p IsStandalone is false. It is usually true when only a fragment of the function is printed. Only print the defs and the opcode if \p SkipOpers is true. Otherwise, also print operands if \p SkipDebugLoc is true. Otherwise, also print the debug loc, with a terminating newline.\p TII is used to print the opcode name. If it's not present, but the MI is in a function, the opcode will be printed using the function's TII.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1525

Parameters

llvm::raw_ostream& OS
bool IsStandalone = true
bool SkipOpers = false
bool SkipDebugLoc = false
bool AddNewLine = true
const llvm::TargetInstrInfo* TII = nullptr

void print(llvm::raw_ostream& OS,
           llvm::ModuleSlotTracker& MST,
           bool IsStandalone = true,
           bool SkipOpers = false,
           bool SkipDebugLoc = false,
           bool AddNewLine = true,
           const llvm::TargetInstrInfo* TII =
               nullptr) const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1528

Parameters

llvm::raw_ostream& OS
llvm::ModuleSlotTracker& MST
bool IsStandalone = true
bool SkipOpers = false
bool SkipDebugLoc = false
bool AddNewLine = true
const llvm::TargetInstrInfo* TII = nullptr

bool readsRegister(llvm::Register Reg,
                   const llvm::TargetRegisterInfo*
                       TRI = nullptr) const

Description

Return true if the MachineInstr reads the specified register. If TargetRegisterInfo is passed, then it also checks if there is a read of a super-register. This does not count partial redefines of virtual registers as reads: %reg1024:6 = OP.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1188

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* TRI = nullptr

bool readsVirtualRegister(
    llvm::Register Reg) const

Description

Return true if the MachineInstr reads the specified virtual register. Take into account that a partial define is a read-modify-write operation.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1196

Parameters

llvm::Register Reg

std::pair<bool, bool> readsWritesVirtualRegister(
    llvm::Register Reg,
    SmallVectorImpl<unsigned int>* Ops =
        nullptr) const

Description

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. This also considers partial defines. If Ops is not null, all operand indices for Reg are added.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1203

Parameters

llvm::Register Reg
SmallVectorImpl<unsigned int>* Ops = nullptr

bool registerDefIsDead(
    llvm::Register Reg,
    const llvm::TargetRegisterInfo* TRI =
        nullptr) const

Description

Returns true if the register is dead in this machine instruction. If TargetRegisterInfo is passed, then it also checks if there is a dead def of a super-register.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1233

Parameters

llvm::Register Reg
const llvm::TargetRegisterInfo* TRI = nullptr

llvm::MachineInstr* removeFromBundle()

Description

Unlink this instruction from its basic block and return it without deleting it. If the instruction is part of a bundle, the other instructions in the bundle remain bundled.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1018

llvm::MachineInstr* removeFromParent()

Description

Unlink 'this' from the containing basic block, and return it without deleting it. This function can not be used on bundled instructions, use removeFromBundle() to remove individual instructions from a bundle.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1011

void setAsmPrinterFlag(uint8_t Flag)

Description

Set a flag for the AsmPrinter.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:297

Parameters

uint8_t Flag

void setDebugLoc(llvm::DebugLoc dl)

Description

Replace current source information with new such. Avoid using this, the constructor argument is preferable.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1563

Parameters

llvm::DebugLoc dl

void setDesc(const llvm::MCInstrDesc& tid)

Description

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1559

Parameters

const llvm::MCInstrDesc& tid

void setFlag(llvm::MachineInstr::MIFlag Flag)

Description

Set a MI flag.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:317

Parameters

llvm::MachineInstr::MIFlag Flag

void setFlags(unsigned int flags)

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:321

Parameters

unsigned int flags

void setHeapAllocMarker(llvm::MachineFunction& MF,
                        llvm::MDNode* MD)

Description

Set a marker on instructions that denotes where we should create and emit heap alloc site labels. This waits until after instruction selection and optimizations to create the label, so it should still work if the instruction is removed or duplicated.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1630

Parameters

llvm::MachineFunction& MF
llvm::MDNode* MD

void setMemRefs(
    llvm::MachineFunction& MF,
    ArrayRef<llvm::MachineMemOperand*> MemRefs)

Description

Assign this MachineInstr's memory reference descriptor list. Unlike other methods, this *will* allocate them into a new array associated with the provided `MachineFunction`.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1582

Parameters

llvm::MachineFunction& MF
ArrayRef<llvm::MachineMemOperand*> MemRefs

void setPhysRegsDeadExcept(
    ArrayRef<llvm::Register> UsedRegs,
    const llvm::TargetRegisterInfo& TRI)

Description

Mark every physreg used by this instruction as dead except those in the UsedRegs list. On instructions with register mask operands, also add implicit-def operands for all registers in UsedRegs.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1434

Parameters

ArrayRef<llvm::Register> UsedRegs
const llvm::TargetRegisterInfo& TRI

void setPostInstrSymbol(llvm::MachineFunction& MF,
                        llvm::MCSymbol* Symbol)

Description

Set a symbol that will be emitted just after the instruction itself. Setting this to a null pointer will remove any such symbol. FIXME: This is not fully implemented yet.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1620

Parameters

llvm::MachineFunction& MF
llvm::MCSymbol* Symbol

void setPreInstrSymbol(llvm::MachineFunction& MF,
                       llvm::MCSymbol* Symbol)

Description

Set a symbol that will be emitted just prior to the instruction itself. Setting this to a null pointer will remove any such symbol. FIXME: This is not fully implemented yet.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1613

Parameters

llvm::MachineFunction& MF
llvm::MCSymbol* Symbol

void setRegisterDefReadUndef(llvm::Register Reg,
                             bool IsUndef = true)

Description

Mark all subregister defs of register @p Reg with the undef flag. This function is used when we determined to have a subregister def in an otherwise undefined super register.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1422

Parameters

llvm::Register Reg
bool IsUndef = true

void substituteRegister(
    llvm::Register FromReg,
    llvm::Register ToReg,
    unsigned int SubIdx,
    const llvm::TargetRegisterInfo& RegInfo)

Description

Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1394

Parameters

llvm::Register FromReg
llvm::Register ToReg
unsigned int SubIdx
const llvm::TargetRegisterInfo& RegInfo

void tieOperands(unsigned int DefIdx,
                 unsigned int UseIdx)

Description

Add a tie between the register operands at DefIdx and UseIdx. The tie will cause the register allocator to ensure that the two operands are assigned the same physical register. Tied operands are managed automatically for explicit operands in the MCInstrDesc. This method is for exceptional cases like inline asm.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1355

Parameters

unsigned int DefIdx
unsigned int UseIdx

void unbundleFromPred()

Description

Break bundle above this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:394

void unbundleFromSucc()

Description

Break bundle below this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:397

void untieRegOperand(unsigned int OpIdx)

Description

Break any tie involving OpIdx.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:1643

Parameters

unsigned int OpIdx

iterator_range<
    llvm::MachineInstr::const_mop_iterator>
uses() const

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:529

iterator_range<llvm::MachineInstr::mop_iterator>
uses()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:525

bool usesCustomInsertionHook(
    llvm::MachineInstr::QueryType Type =
        IgnoreBundle) const

Description

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed. If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:938

Parameters

llvm::MachineInstr::QueryType Type = IgnoreBundle

~MachineInstr()

Declared at: llvm/include/llvm/CodeGen/MachineInstr.h:269