class SDep

Declaration

class SDep { /* full declaration omitted */ };

Description

Scheduling dependency. This represents one direction of an edge in the scheduling DAG.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:49

Method Overview

Methods

SDep(llvm::SUnit* S,
     llvm::SDep::Kind kind,
     unsigned int Reg)

Description

Constructs an SDep with the specified values.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:104

Parameters

llvm::SUnit* S
llvm::SDep::Kind kind
unsigned int Reg

SDep(llvm::SUnit* S, llvm::SDep::OrderKind kind)

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:123

Parameters

llvm::SUnit* S
llvm::SDep::OrderKind kind

SDep()

Description

Constructs a null SDep. This is only for use by container classes which require default constructors. SUnits may not/ have null SDep edges.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:101

void dump(const llvm::TargetRegisterInfo* TRI =
              nullptr) const

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:238

Parameters

const llvm::TargetRegisterInfo* TRI = nullptr

llvm::SDep::Kind getKind() const

Description

Returns an enum value representing the kind of the dependence.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:158

unsigned int getLatency() const

Description

Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:142

unsigned int getReg() const

Description

Returns the register associated with this edge. This is only valid on Data, Anti, and Output edges. On Data edges, this value may be zero, meaning there is no associated register.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:218

llvm::SUnit* getSUnit() const

Description

/ Returns the SUnit to which this edge points.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:152

bool isArtificial() const

Description

Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:200

bool isAssignedRegDep() const

Description

Tests if this is a Data dependence that is associated with a register.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:211

bool isBarrier() const

Description

Tests if this is an Order dependence that is marked as a barrier.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:174

bool isCluster() const

Description

Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:206

bool isCtrl() const

Description

Shorthand for getKind() != SDep::Data.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:161

bool isMustAlias() const

Description

Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:186

bool isNormalMemory() const

Description

Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:168

bool isNormalMemoryOrBarrier() const

Description

Tests if this is could be any kind of memory dependence.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:179

bool isWeak() const

Description

Tests if this a weak dependence. Weak dependencies are considered DAG edges for height computation and other heuristics, but do not force ordering. Breaking a weak edge may require the scheduler to compensate, for example by inserting a copy.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:194

bool overlaps(const llvm::SDep& Other) const

Description

Returns true if the specified SDep is equivalent except for latency.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:129

Parameters

const llvm::SDep& Other

void setLatency(unsigned int Lat)

Description

Sets the latency for this edge.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:147

Parameters

unsigned int Lat

void setReg(unsigned int Reg)

Description

Assigns the associated register for this edge. This is only valid on Data, Anti, and Output edges. On Anti and Output edges, this value must not be zero. On Data edges, the value may be zero, which would mean that no specific register is associated with this edge.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:228

Parameters

unsigned int Reg

void setSUnit(llvm::SUnit* SU)

Description

/ Assigns the SUnit to which this edge points.

Declared at: llvm/include/llvm/CodeGen/ScheduleDAG.h:155

Parameters

llvm::SUnit* SU