class MCSubtargetInfo

Declaration

class MCSubtargetInfo { /* full declaration omitted */ };

Description

Generic base class for all target subtargets.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:74

Method Overview

Methods

llvm::FeatureBitset ApplyFeatureFlag(
    llvm::StringRef FS)

Description

Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:142

Parameters

llvm::StringRef FS

llvm::FeatureBitset ClearFeatureBitsTransitively(
    const llvm::FeatureBitset& FB)

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:146

Parameters

const llvm::FeatureBitset& FB

void InitMCProcessorInfo(llvm::StringRef CPU,
                         llvm::StringRef FS)

Description

Initialize the scheduling model and feature bits. FIXME: Find a way to stick this in the constructor, since it should only be called during initialization.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:121

Parameters

llvm::StringRef CPU
llvm::StringRef FS

MCSubtargetInfo(
    const llvm::Triple& TT,
    llvm::StringRef CPU,
    llvm::StringRef FS,
    ArrayRef<llvm::SubtargetFeatureKV> PF,
    ArrayRef<llvm::SubtargetSubTypeKV> PD,
    const llvm::MCWriteProcResEntry* WPR,
    const llvm::MCWriteLatencyEntry* WL,
    const llvm::MCReadAdvanceEntry* RA,
    const llvm::InstrStage* IS,
    const unsigned int* OC,
    const unsigned int* FP)

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:93

Parameters

const llvm::Triple& TT
llvm::StringRef CPU
llvm::StringRef FS
ArrayRef<llvm::SubtargetFeatureKV> PF
ArrayRef<llvm::SubtargetSubTypeKV> PD
const llvm::MCWriteProcResEntry* WPR
const llvm::MCWriteLatencyEntry* WL
const llvm::MCReadAdvanceEntry* RA
const llvm::InstrStage* IS
const unsigned int* OC
const unsigned int* FP

MCSubtargetInfo()

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:99

MCSubtargetInfo(const llvm::MCSubtargetInfo&)

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:92

Parameters

const llvm::MCSubtargetInfo& 

llvm::FeatureBitset SetFeatureBitsTransitively(
    const llvm::FeatureBitset& FB)

Description

Set/clear additional feature bits, including all other bits they imply.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:145

Parameters

const llvm::FeatureBitset& FB

llvm::FeatureBitset ToggleFeature(
    llvm::StringRef FS)

Description

Toggle a set of features and return the re-computed feature bits. This version will also change all implied bits.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:138

Parameters

llvm::StringRef FS

llvm::FeatureBitset ToggleFeature(uint64_t FB)

Description

Toggle a feature and return the re-computed feature bits. This version does not change the implied bits.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:130

Parameters

uint64_t FB

llvm::FeatureBitset ToggleFeature(
    const llvm::FeatureBitset& FB)

Description

Toggle a feature and return the re-computed feature bits. This version does not change the implied bits.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:134

Parameters

const llvm::FeatureBitset& FB

bool checkFeatures(llvm::StringRef FS) const

Description

Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:150

Parameters

llvm::StringRef FS

llvm::StringRef getCPU() const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:105

virtual Optional<unsigned int>
getCacheAssociativity(unsigned int Level) const

Description

Return the cache associatvity for the given level of cache. Level is zero-based, so a value of zero means the first level of cache.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:237

Parameters

unsigned int Level

virtual Optional<unsigned int> getCacheLineSize(
    unsigned int Level) const

Description

Return the target cache line size in bytes at a given level.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:241

Parameters

unsigned int Level

virtual unsigned int getCacheLineSize() const

Description

Return the target cache line size in bytes. By default, return the line size for the bottom-most level of cache. This provides a more convenient interface for the common case where all cache levels have the same line size. Return zero if there is no cache model.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:249

virtual Optional<unsigned int> getCacheSize(
    unsigned int Level) const

Description

Return the cache size in bytes for the given level of cache. Level is zero-based, so a value of zero means the first level of cache.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:231

Parameters

unsigned int Level

const llvm::FeatureBitset& getFeatureBits() const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:107

virtual unsigned int getHwMode() const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:225

llvm::InstrItineraryData getInstrItineraryForCPU(
    llvm::StringRef CPU) const

Description

Get scheduling itinerary of a CPU.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:207

Parameters

llvm::StringRef CPU

virtual unsigned int
getMaxPrefetchIterationsAhead() const

Description

Return the maximum prefetch distance in terms of loop iterations.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:264

virtual unsigned int getMinPrefetchStride() const

Description

Return the minimum stride necessary to trigger software prefetching.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:269

virtual unsigned int getPrefetchDistance() const

Description

Return the preferred prefetch distance in terms of instructions.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:259

int getReadAdvanceCycles(
    const llvm::MCSchedClassDesc* SC,
    unsigned int UseIdx,
    unsigned int WriteResID) const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:177

Parameters

const llvm::MCSchedClassDesc* SC
unsigned int UseIdx
unsigned int WriteResID

ArrayRef<llvm::MCReadAdvanceEntry>
getReadAdvanceEntries(
    const llvm::MCSchedClassDesc& SC) const

Description

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:199

Parameters

const llvm::MCSchedClassDesc& SC

const llvm::MCSchedModel& getSchedModel() const

Description

Get the machine model for this subtarget's CPU.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:156

const llvm::MCSchedModel& getSchedModelForCPU(
    llvm::StringRef CPU) const

Description

Get the machine model of a CPU.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:153

Parameters

llvm::StringRef CPU

const llvm::Triple& getTargetTriple() const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:104

const llvm::MCWriteLatencyEntry*
getWriteLatencyEntry(
    const llvm::MCSchedClassDesc* SC,
    unsigned int DefIdx) const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:169

Parameters

const llvm::MCSchedClassDesc* SC
unsigned int DefIdx

const llvm::MCWriteProcResEntry*
getWriteProcResBegin(
    const llvm::MCSchedClassDesc* SC) const

Description

Return an iterator at the first process resource consumed by the given scheduling class.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:160

Parameters

const llvm::MCSchedClassDesc* SC

const llvm::MCWriteProcResEntry*
getWriteProcResEnd(
    const llvm::MCSchedClassDesc* SC) const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:164

Parameters

const llvm::MCSchedClassDesc* SC

bool hasFeature(unsigned int Feature) const

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:112

Parameters

unsigned int Feature

void initInstrItins(
    llvm::InstrItineraryData& InstrItins) const

Description

Initialize an InstrItineraryData instance.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:210

Parameters

llvm::InstrItineraryData& InstrItins

bool isCPUStringValid(llvm::StringRef CPU) const

Description

Check whether the CPU string is valid.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:220

Parameters

llvm::StringRef CPU

virtual unsigned int resolveVariantSchedClass(
    unsigned int SchedClass,
    const llvm::MCInst* MI,
    unsigned int CPUID) const

Description

Resolve a variant scheduling class for the given MCInst and CPU.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:214

Parameters

unsigned int SchedClass
const llvm::MCInst* MI
unsigned int CPUID

void setDefaultFeatures(llvm::StringRef CPU,
                        llvm::StringRef FS)

Description

Set the features to the default for the given CPU with an appended feature string.

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:126

Parameters

llvm::StringRef CPU
llvm::StringRef FS

void setFeatureBits(
    const llvm::FeatureBitset& FeatureBits_)

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:108

Parameters

const llvm::FeatureBitset& FeatureBits_

virtual ~MCSubtargetInfo()

Declared at: llvm/include/llvm/MC/MCSubtargetInfo.h:102