class TargetRegisterClass

Declaration

class TargetRegisterClass { /* full declaration omitted */ };

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:44

Member Variables

public const llvm::MCRegisterClass* MC
public const uint32_t* SubClassMask
public const uint16_t* SuperRegIndices
public const llvm::LaneBitmask LaneMask
public const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heuristic. The value is in the range [0,63].
public const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
public const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class. See also the CoveredBySubRegs description in Target.td.
public const llvm::TargetRegisterClass::sc_iterator SuperClasses
public ArrayRef<llvm::MCPhysReg> (*)( const llvm::MachineFunction&) OrderFunc

Method Overview

Methods

llvm::TargetRegisterClass::iterator begin() const

Description

begin/end - Return all of the registers in this class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:71

bool contains(unsigned int Reg1,
              unsigned int Reg2) const

Description

Return true if both registers are in this class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:98

Parameters

unsigned int Reg1
unsigned int Reg2

bool contains(unsigned int Reg) const

Description

Return true if the specified register is included in this register class. This does not include virtual registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:89

Parameters

unsigned int Reg

llvm::TargetRegisterClass::iterator end() const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:72

int getCopyCost() const

Description

Return the cost of copying a value between two registers in this class. A negative number means the register class is very expensive to copy e.g. status flag register classes.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:110

unsigned int getID() const

Description

Return the register class ID number.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:67

llvm::LaneBitmask getLaneMask() const

Description

Returns the combination of all lane masks of register in this class. The lane masks of the registers are the combination of all lane masks of their subregisters. Returns 1 if there are no subregisters.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:203

unsigned int getNumRegs() const

Description

Return the number of registers in this class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:75

ArrayRef<llvm::MCPhysReg> getRawAllocationOrder(
    const llvm::MachineFunction& MF) const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:196

Parameters

const llvm::MachineFunction& MF

unsigned int getRegister(unsigned int i) const

Description

Return the specified register in the class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:83

Parameters

unsigned int i

int getRegisters() const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:78

const uint32_t* getSubClassMask() const

Description

I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored. See the implementation of hasSubClassEq for an example of how it can be used.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:155

llvm::TargetRegisterClass::sc_iterator
getSuperClasses() const

Description

Returns a NULL-terminated list of super-classes. The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:173

const uint16_t* getSuperRegIndices() const

Description

Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. The list has an entry for each Idx such that: There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:166

bool hasSubClass(
    const llvm::TargetRegisterClass* RC) const

Description

Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:118

Parameters

const llvm::TargetRegisterClass* RC

bool hasSubClassEq(
    const llvm::TargetRegisterClass* RC) const

Description

Returns true if RC is a sub-class of or equal to this class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:123

Parameters

const llvm::TargetRegisterClass* RC

bool hasSuperClass(
    const llvm::TargetRegisterClass* RC) const

Description

Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:130

Parameters

const llvm::TargetRegisterClass* RC

bool hasSuperClassEq(
    const llvm::TargetRegisterClass* RC) const

Description

Returns true if RC is a super-class of or equal to this class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:135

Parameters

const llvm::TargetRegisterClass* RC

bool isASubClass() const

Description

Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:179

bool isAllocatable() const

Description

Return true if this register class may be used to create virtual registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:114