class TargetLoweringBase

Declaration

class TargetLoweringBase { /* full declaration omitted */ };

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:111

Member Variables

protected unsigned int GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find a more preferable chain. As an approximation, this should be more than the number of consecutive stores expected to be merged.
protected unsigned int MaxStoresPerMemset
When lowering @ llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.
protected unsigned int MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
protected unsigned int MaxStoresPerMemcpy
When lowering @ llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.
protected unsigned int MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
protected unsigned int MaxGluedStoresPerMemcpy = 0
When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number of store instructions to keep together. This helps in pairing and
protected unsigned int MaxLoadsPerMemcmp
When lowering @ llvm.memcmp this field specifies the maximum number of pairs of load operations that may be substituted for a call to memcmp. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcmp will be done using as many of the largest load operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, loading 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte load, a one 2-byte load and one 1-byte load. This only applies to copying a constant array of constant size.
protected unsigned int MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
protected unsigned int MaxStoresPerMemmove
When lowering @ llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.
protected unsigned int MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
protected bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.
protected bool EnableExtLdPromotion
protected bool IsStrictFPEnabled

Method Overview

Methods

void AddPromotedToType(unsigned int Opc,
                       llvm::MVT OrigVT,
                       llvm::MVT DestVT)

Description

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2086

Parameters

unsigned int Opc
llvm::MVT OrigVT
llvm::MVT DestVT

int InstructionOpcodeToISD(
    unsigned int Opcode) const

Description

Get the ISD node that corresponds to the Instruction class opcode.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1672

Parameters

unsigned int Opcode

virtual bool ShouldShrinkFPConstant(
    llvm::EVT) const

Description

If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1358

Parameters

llvm::EVT 

TargetLoweringBase(const llvm::TargetMachine& TM)

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:228

Parameters

const llvm::TargetMachine& TM

TargetLoweringBase(
    const llvm::TargetLoweringBase&)

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:229

Parameters

const llvm::TargetLoweringBase& 

void addBypassSlowDiv(unsigned int SlowBitWidth,
                      unsigned int FastBitWidth)

Description

Tells the code generator which bitwidths to bypass.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1979

Parameters

unsigned int SlowBitWidth
unsigned int FastBitWidth

void addRegisterClass(
    llvm::MVT VT,
    const llvm::TargetRegisterClass* RC)

Description

Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1986

Parameters

llvm::MVT VT
const llvm::TargetRegisterClass* RC

virtual bool aggressivelyPreferBuildVectorSources(
    llvm::EVT VecVT) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2595

Parameters

llvm::EVT VecVT

virtual bool alignLoopsWithOptSize() const

Description

Should loops be aligned even when the function is marked OptSize (but not MinSize).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1601

virtual bool allowTruncateForTailCall(
    llvm::Type* FromTy,
    llvm::Type* ToTy) const

Description

Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy < = ToTy.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2307

Parameters

llvm::Type* FromTy
llvm::Type* ToTy

virtual bool allowsMemoryAccess(
    llvm::LLVMContext& Context,
    const llvm::DataLayout& DL,
    llvm::EVT VT,
    unsigned int AddrSpace = 0,
    unsigned int Alignment = 1,
    MachineMemOperand::Flags Flags =
        MachineMemOperand::MONone,
    bool* Fast = nullptr) const

Description

Return true if the target supports a memory access of this type for the given address space and alignment. If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1492

Parameters

llvm::LLVMContext& Context
const llvm::DataLayout& DL
llvm::EVT VT
unsigned int AddrSpace = 0
unsigned int Alignment = 1
MachineMemOperand::Flags Flags = MachineMemOperand::MONone
bool* Fast = nullptr

bool allowsMemoryAccess(
    llvm::LLVMContext& Context,
    const llvm::DataLayout& DL,
    llvm::EVT VT,
    const llvm::MachineMemOperand& MMO,
    bool* Fast = nullptr) const

Description

Return true if the target supports a memory access of this type for the given MachineMemOperand. If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1501

Parameters

llvm::LLVMContext& Context
const llvm::DataLayout& DL
llvm::EVT VT
const llvm::MachineMemOperand& MMO
bool* Fast = nullptr

bool allowsMemoryAccessForAlignment(
    llvm::LLVMContext& Context,
    const llvm::DataLayout& DL,
    llvm::EVT VT,
    unsigned int AddrSpace = 0,
    unsigned int Alignment = 1,
    MachineMemOperand::Flags Flags =
        MachineMemOperand::MONone,
    bool* Fast = nullptr) const

Description

This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access. If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1472

Parameters

llvm::LLVMContext& Context
const llvm::DataLayout& DL
llvm::EVT VT
unsigned int AddrSpace = 0
unsigned int Alignment = 1
MachineMemOperand::Flags Flags = MachineMemOperand::MONone
bool* Fast = nullptr

bool allowsMemoryAccessForAlignment(
    llvm::LLVMContext& Context,
    const llvm::DataLayout& DL,
    llvm::EVT VT,
    const llvm::MachineMemOperand& MMO,
    bool* Fast = nullptr) const

Description

Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand. If the access is allowed, the optional final parameter returns if the access is also fast (as defined by the target).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1482

Parameters

llvm::LLVMContext& Context
const llvm::DataLayout& DL
llvm::EVT VT
const llvm::MachineMemOperand& MMO
bool* Fast = nullptr

virtual bool allowsMisalignedMemoryAccesses(
    llvm::LLT,
    unsigned int AddrSpace = 0,
    unsigned int Align = 1,
    MachineMemOperand::Flags Flags =
        MachineMemOperand::MONone,
    bool* = nullptr) const

Description

LLT handling variant.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1461

Parameters

llvm::LLT
unsigned int AddrSpace = 0
unsigned int Align = 1
MachineMemOperand::Flags Flags = MachineMemOperand::MONone
bool* = nullptr

virtual bool allowsMisalignedMemoryAccesses(
    llvm::EVT,
    unsigned int AddrSpace = 0,
    unsigned int Align = 1,
    MachineMemOperand::Flags Flags =
        MachineMemOperand::MONone,
    bool* = nullptr) const

Description

Determine if the target supports unaligned memory accesses. This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns whether the unaligned memory access is "fast" in the last argument by reference. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1453

Parameters

llvm::EVT
unsigned int AddrSpace = 0
unsigned int Align = 1
MachineMemOperand::Flags Flags = MachineMemOperand::MONone
bool* = nullptr

virtual bool areJTsAllowed(
    const llvm::Function* Fn) const

Description

Return true if lowering to a jump table is allowed.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:998

Parameters

const llvm::Function* Fn

virtual bool canCombineStoreAndExtract(
    llvm::Type* VectorTy,
    llvm::Value* Idx,
    unsigned int& Cost) const

Description

Return true if the target can combine store(extractelement VectorTy, Idx).\p Cost[out] gives the cost of that transformation when this is true.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:642

Parameters

llvm::Type* VectorTy
llvm::Value* Idx
unsigned int& Cost

virtual bool canMergeStoresTo(
    unsigned int AS,
    llvm::EVT MemVT,
    const llvm::SelectionDAG& DAG) const

Description

Returns if it's reasonable to merge stores to MemVT size.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:459

Parameters

unsigned int AS
llvm::EVT MemVT
const llvm::SelectionDAG& DAG

virtual bool canOpTrap(unsigned int Op,
                       llvm::EVT VT) const

Description

Returns true if the operation can trap for the value type. VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:889

Parameters

unsigned int Op
llvm::EVT VT

void computeRegisterProperties(
    const llvm::TargetRegisterInfo* TRI)

Description

Once all of the register classes are added, this allows us to compute derived properties we expose.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1998

Parameters

const llvm::TargetRegisterInfo* TRI

virtual bool convertSelectOfConstantsToMath(
    llvm::EVT VT) const

Description

Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. For example: select Cond, C1, C1-1 --> add (zext Cond), C1-1

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1889

Parameters

llvm::EVT VT

virtual bool convertSetCCLogicToBitwiseLogic(
    llvm::EVT VT) const

Description

Use bitwise logic to make pairs of compares more efficient. For example: and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:516

Parameters

llvm::EVT VT

virtual bool decomposeMulByConstant(
    llvm::LLVMContext& Context,
    llvm::EVT VT,
    llvm::SDValue C) const

Description

Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1898

Parameters

llvm::LLVMContext& Context
llvm::EVT VT
llvm::SDValue C

virtual void emitAtomicCmpXchgNoStoreLLBalance(
    int& Builder) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1804

Parameters

int& Builder

virtual llvm::Instruction* emitLeadingFence(
    int& Builder,
    llvm::Instruction* Inst,
    llvm::AtomicOrdering Ord) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1780

Parameters

int& Builder
llvm::Instruction* Inst
llvm::AtomicOrdering Ord

virtual llvm::Value* emitLoadLinked(
    int& Builder,
    llvm::Value* Addr,
    llvm::AtomicOrdering Ord) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1715

Parameters

int& Builder
llvm::Value* Addr
llvm::AtomicOrdering Ord

virtual llvm::Value*
emitMaskedAtomicCmpXchgIntrinsic(
    int& Builder,
    llvm::AtomicCmpXchgInst* CI,
    llvm::Value* AlignedAddr,
    llvm::Value* CmpVal,
    llvm::Value* NewVal,
    llvm::Value* Mask,
    llvm::AtomicOrdering Ord) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1741

Parameters

int& Builder
llvm::AtomicCmpXchgInst* CI
llvm::Value* AlignedAddr
llvm::Value* CmpVal
llvm::Value* NewVal
llvm::Value* Mask
llvm::AtomicOrdering Ord

virtual llvm::Value* emitMaskedAtomicRMWIntrinsic(
    int& Builder,
    llvm::AtomicRMWInst* AI,
    llvm::Value* AlignedAddr,
    llvm::Value* Incr,
    llvm::Value* Mask,
    llvm::Value* ShiftAmt,
    llvm::AtomicOrdering Ord) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1730

Parameters

int& Builder
llvm::AtomicRMWInst* AI
llvm::Value* AlignedAddr
llvm::Value* Incr
llvm::Value* Mask
llvm::Value* ShiftAmt
llvm::AtomicOrdering Ord

llvm::MachineBasicBlock* emitPatchPoint(
    llvm::MachineInstr& MI,
    llvm::MachineBasicBlock* MBB) const

Description

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2932

Parameters

llvm::MachineInstr& MI
llvm::MachineBasicBlock* MBB

virtual llvm::Value* emitStoreConditional(
    int& Builder,
    llvm::Value* Val,
    llvm::Value* Addr,
    llvm::AtomicOrdering Ord) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1722

Parameters

int& Builder
llvm::Value* Val
llvm::Value* Addr
llvm::AtomicOrdering Ord

virtual llvm::Instruction* emitTrailingFence(
    int& Builder,
    llvm::Instruction* Inst,
    llvm::AtomicOrdering Ord) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1788

Parameters

int& Builder
llvm::Instruction* Inst
llvm::AtomicOrdering Ord

llvm::MachineBasicBlock* emitXRayCustomEvent(
    llvm::MachineInstr& MI,
    llvm::MachineBasicBlock* MBB) const

Description

Replace/modify the XRay custom event operands with target-dependent details.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2937

Parameters

llvm::MachineInstr& MI
llvm::MachineBasicBlock* MBB

llvm::MachineBasicBlock* emitXRayTypedEvent(
    llvm::MachineInstr& MI,
    llvm::MachineBasicBlock* MBB) const

Description

Replace/modify the XRay typed event operands with target-dependent details.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2942

Parameters

llvm::MachineInstr& MI
llvm::MachineBasicBlock* MBB

virtual bool enableAggressiveFMAFusion(
    llvm::EVT VT) const

Description

Return true if target always beneficiates from combining into FMA for a given value type. This must typically return false on targets where FMA takes more cycles to execute than FADD.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:656

Parameters

llvm::EVT VT

bool enableExtLdPromotion() const

Description

Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:637

virtual void finalizeLowering(
    llvm::MachineFunction& MF) const

Description

Execute target specific actions to finalize target lowering. This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2650

Parameters

llvm::MachineFunction& MF

virtual std::pair<const TargetRegisterClass*,
                  uint8_t>
findRepresentativeClass(
    const llvm::TargetRegisterInfo* TRI,
    llvm::MVT VT) const

Description

Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1994

Parameters

const llvm::TargetRegisterInfo* TRI
llvm::MVT VT

virtual llvm::Align getABIAlignmentForCallingConv(
    llvm::Type* ArgTy,
    llvm::DataLayout DL) const

Description

Certain targets have context senstive alignment requirements, where one type has the alignment requirement of another type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1350

Parameters

llvm::Type* ArgTy
llvm::DataLayout DL

virtual bool getAddrModeArguments(
    llvm::IntrinsicInst*,
    SmallVectorImpl<llvm::Value*>&,
    llvm::Type*&) const

Description

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2154

Parameters

llvm::IntrinsicInst*
SmallVectorImpl<llvm::Value*>&
llvm::Type*& 

llvm::TargetLoweringBase::BooleanContent
getBooleanContents(llvm::EVT Type) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:689

Parameters

llvm::EVT Type

llvm::TargetLoweringBase::BooleanContent
getBooleanContents(bool isVec, bool isFloat) const

Description

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. "Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1. Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:683

Parameters

bool isVec
bool isFloat

virtual unsigned int getByValTypeAlignment(
    llvm::Type* Ty,
    const llvm::DataLayout& DL) const

Description

Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. This is the actual alignment, not its logarithm.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1274

Parameters

llvm::Type* Ty
const llvm::DataLayout& DL

const int& getBypassSlowDivWidths() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:388

ISD::CondCode getCmpLibcallCC(
    RTLIB::Libcall Call) const

Description

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2632

Parameters

RTLIB::Libcall Call

virtual MVT::SimpleValueType
getCmpLibcallReturnType() const

Description

Return the ValueType for comparison libcalls. Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:668

llvm::TargetLoweringBase::LegalizeAction
getCondCodeAction(ISD::CondCode CC,
                  llvm::MVT VT) const

Description

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1173

Parameters

ISD::CondCode CC
llvm::MVT VT

llvm::Value* getDefaultSafeStackPointerLocation(
    int& IRB,
    bool UseTLS) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1633

Parameters

int& IRB
bool UseTLS

int getDivRefinementSteps(
    llvm::EVT VT,
    llvm::MachineFunction& MF) const

Description

Return the refinement step count for a division of the given type based on the function's attributes. If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:381

Parameters

llvm::EVT VT
llvm::MachineFunction& MF

virtual unsigned int getExceptionPointerRegister(
    const llvm::Constant* PersonalityFn) const

Description

If a physical register, this returns the register that receives the exception address on entry to an EH pad.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1566

Parameters

const llvm::Constant* PersonalityFn

virtual unsigned int getExceptionSelectorRegister(
    const llvm::Constant* PersonalityFn) const

Description

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1574

Parameters

const llvm::Constant* PersonalityFn

virtual ISD::NodeType getExtendForAtomicOps()
    const

Description

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1860

static ISD::NodeType getExtendForContent(
    llvm::TargetLoweringBase::BooleanContent
        Content)

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:213

Parameters

llvm::TargetLoweringBase::BooleanContent Content

virtual llvm::MVT getFenceOperandTy(
    const llvm::DataLayout& DL) const

Description

Return the type for operands of fence. TODO: Let fence operands be of i32 type and remove this.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:269

Parameters

const llvm::DataLayout& DL

llvm::TargetLoweringBase::LegalizeAction
getFixedPointOperationAction(
    unsigned int Op,
    llvm::EVT VT,
    unsigned int Scale) const

Description

Some fixed point operations may be natively supported by the target but only for specific scales. This method allows for checking if the width is supported by the target for a given operation that may depend on scale.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:922

Parameters

unsigned int Op
llvm::EVT VT
unsigned int Scale

llvm::MVT getFrameIndexTy(
    const llvm::DataLayout& DL) const

Description

Return the type for frame index, which is determined by the alloca address space specified through the data layout.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:263

Parameters

const llvm::DataLayout& DL

unsigned int getGatherAllAliasesMaxDepth() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1386

virtual llvm::Value* getIRStackGuard(
    int& IRB) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1609

Parameters

int& IRB

llvm::TargetLoweringBase::LegalizeAction
getIndexedLoadAction(unsigned int IdxMode,
                     llvm::MVT VT) const

Description

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1116

Parameters

unsigned int IdxMode
llvm::MVT VT

llvm::TargetLoweringBase::LegalizeAction
getIndexedMaskedLoadAction(unsigned int IdxMode,
                           llvm::MVT VT) const

Description

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1144

Parameters

unsigned int IdxMode
llvm::MVT VT

llvm::TargetLoweringBase::LegalizeAction
getIndexedMaskedStoreAction(unsigned int IdxMode,
                            llvm::MVT VT) const

Description

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1158

Parameters

unsigned int IdxMode
llvm::MVT VT

llvm::TargetLoweringBase::LegalizeAction
getIndexedStoreAction(unsigned int IdxMode,
                      llvm::MVT VT) const

Description

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1130

Parameters

unsigned int IdxMode
llvm::MVT VT

CallingConv::ID getLibcallCallingConv(
    RTLIB::Libcall Call) const

Description

Get the CallingConv that should be used for the specified libcall.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2642

Parameters

RTLIB::Libcall Call

const char* getLibcallName(
    RTLIB::Libcall Call) const

Description

Get the libcall routine name for the specified libcall.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2620

Parameters

RTLIB::Libcall Call

llvm::TargetLoweringBase::LegalizeAction
getLoadExtAction(unsigned int ExtType,
                 llvm::EVT ValVT,
                 llvm::EVT MemVT) const

Description

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1064

Parameters

unsigned int ExtType
llvm::EVT ValVT
llvm::EVT MemVT

unsigned int getMaxAtomicSizeInBitsSupported()
    const

Description

Returns the maximum atomic operation size (in bits) supported by the backend. Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1688

unsigned int getMaxExpandSizeMemcmp(
    bool OptSize) const

Description

Get maximum # of load operations permitted for memcmp This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1430

Parameters

bool OptSize

virtual unsigned int getMaxGluedStoresPerMemcpy()
    const

Description

Get maximum # of store operations to be glued together

This function returns the maximum number of store operations permitted to glue together during lowering of llvm.memcpy. The value is set by

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1420

unsigned int getMaxStoresPerMemcpy(
    bool OptSize) const

Description

Get maximum # of store operations permitted for llvm.memcpy This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1411

Parameters

bool OptSize

unsigned int getMaxStoresPerMemmove(
    bool OptSize) const

Description

Get maximum # of store operations permitted for llvm.memmove This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1440

Parameters

bool OptSize

unsigned int getMaxStoresPerMemset(
    bool OptSize) const

Description

Get maximum # of store operations permitted for llvm.memset This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1401

Parameters

bool OptSize

virtual unsigned int
getMaxSupportedInterleaveFactor() const

Description

Get the maximum supported factor for interleaved memory accesses. Default to be the minimum interleave factor: 2.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2439

unsigned int getMaximumJumpTableSize() const

Description

Return upper limit for number of entries in a jump table. Zero if no limit.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1551

llvm::EVT getMemValueType(
    const llvm::DataLayout& DL,
    llvm::Type* Ty,
    bool AllowUnknown = false) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1246

Parameters

const llvm::DataLayout& DL
llvm::Type* Ty
bool AllowUnknown = false

unsigned int getMinCmpXchgSizeInBits() const

Description

Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. Any smaller operations are widened in AtomicExpandPass. Note that *unlike* operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1699

llvm::Align getMinFunctionAlignment() const

Description

Return the minimum function alignment.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1589

llvm::Align getMinStackArgumentAlignment() const

Description

Return the minimum stack alignment of an argument.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1584

unsigned int getMinimumJumpTableDensity(
    bool OptForSize) const

Description

Return lower limit of the density in a jump table.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1547

Parameters

bool OptForSize

virtual unsigned int getMinimumJumpTableEntries()
    const

Description

Return lower limit for number of blocks in a jump table.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1544

unsigned int getNumRegisters(
    llvm::LLVMContext& Context,
    llvm::EVT VT) const

Description

Return the number of registers that this ValueType will eventually require. This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1311

Parameters

llvm::LLVMContext& Context
llvm::EVT VT

virtual unsigned int
getNumRegistersForCallingConv(
    llvm::LLVMContext& Context,
    CallingConv::ID CC,
    llvm::EVT VT) const

Description

Certain targets require unusual breakdowns of certain types. For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1342

Parameters

llvm::LLVMContext& Context
CallingConv::ID CC
llvm::EVT VT

llvm::TargetLoweringBase::LegalizeAction
getOperationAction(unsigned int Op,
                   llvm::EVT VT) const

Description

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:902

Parameters

unsigned int Op
llvm::EVT VT

virtual llvm::LLT getOptimalMemOpLLT(
    uint64_t,
    unsigned int,
    unsigned int,
    bool,
    bool,
    bool,
    const llvm::AttributeList&) const

Description

LLT returning variant.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1527

Parameters

uint64_t
unsigned int
unsigned int
bool
bool
bool
const llvm::AttributeList& 

virtual llvm::EVT getOptimalMemOpType(
    uint64_t,
    unsigned int,
    unsigned int,
    bool,
    bool,
    bool,
    const llvm::AttributeList&) const

Description

Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1517

Parameters

uint64_t
unsigned int
unsigned int
bool
bool
bool
const llvm::AttributeList& 

llvm::MVT getPointerMemTy(
    const llvm::DataLayout& DL,
    uint32_t AS = 0) const

Description

Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:257

Parameters

const llvm::DataLayout& DL
uint32_t AS = 0

virtual llvm::MVT getPointerTy(
    const llvm::DataLayout& DL,
    uint32_t AS = 0) const

Description

Return the pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:250

Parameters

const llvm::DataLayout& DL
uint32_t AS = 0

virtual llvm::BranchProbability
getPredictableBranchThreshold() const

Description

If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:404

llvm::Align getPrefFunctionAlignment() const

Description

Return the preferred function alignment.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1592

virtual llvm::Align getPrefLoopAlignment(
    llvm::MachineLoop* ML = nullptr) const

Description

Return the preferred loop alignment.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1595

Parameters

llvm::MachineLoop* ML = nullptr

virtual TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(llvm::MVT VT) const

Description

Return the preferred vector type legalization action.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:309

Parameters

llvm::MVT VT

int getRecipEstimateDivEnabled(
    llvm::EVT VT,
    llvm::MachineFunction& MF) const

Description

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:369

Parameters

llvm::EVT VT
llvm::MachineFunction& MF

int getRecipEstimateSqrtEnabled(
    llvm::EVT VT,
    llvm::MachineFunction& MF) const

Description

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:363

Parameters

llvm::EVT VT
llvm::MachineFunction& MF

virtual const llvm::TargetRegisterClass*
getRegClassFor(llvm::MVT VT,
               bool isDivergent = false) const

Description

Return the register class that should be used for the specified value type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:707

Parameters

llvm::MVT VT
bool isDivergent = false

llvm::MVT getRegisterType(llvm::MVT VT) const

Description

Return the type of registers that this ValueType will eventually require.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1277

Parameters

llvm::MVT VT

llvm::MVT getRegisterType(
    llvm::LLVMContext& Context,
    llvm::EVT VT) const

Description

Return the type of registers that this ValueType will eventually require.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1283

Parameters

llvm::LLVMContext& Context
llvm::EVT VT

virtual llvm::MVT getRegisterTypeForCallingConv(
    llvm::LLVMContext& Context,
    CallingConv::ID CC,
    llvm::EVT VT) const

Description

Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. For MIPS all vector types must be passed through the integer register set.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1334

Parameters

llvm::LLVMContext& Context
CallingConv::ID CC
llvm::EVT VT

virtual uint8_t getRepRegClassCostFor(
    llvm::MVT VT) const

Description

Return the cost of the 'representative' register class for the specified value type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:736

Parameters

llvm::MVT VT

virtual const llvm::TargetRegisterClass*
getRepRegClassFor(llvm::MVT VT) const

Description

Return the 'representative' register class for the specified value type. The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:729

Parameters

llvm::MVT VT

virtual llvm::Value* getSDagStackGuard(
    const llvm::Module& M) const

Description

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. Should be used only when getIRStackGuard returns nullptr.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1618

Parameters

const llvm::Module& M

virtual llvm::Function* getSSPStackGuardCheck(
    const llvm::Module& M) const

Description

If the target has a standard stack protection check function that performs validation and error handling, returns the function. Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1630

Parameters

const llvm::Module& M

virtual llvm::Value* getSafeStackPointerLocation(
    int& IRB) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1638

Parameters

int& IRB

virtual llvm::MVT getScalarShiftAmountTy(
    const llvm::DataLayout&,
    llvm::EVT) const

Description

EVT is not used in-tree, but is used by out-of-tree target. A documentation for this function would be nice...

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:275

Parameters

const llvm::DataLayout&
llvm::EVT 

virtual int getScalingFactorCost(
    const llvm::DataLayout& DL,
    const llvm::TargetLoweringBase::AddrMode& AM,
    llvm::Type* Ty,
    unsigned int AS = 0) const

Description

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well. TODO: Remove default argument

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2196

Parameters

const llvm::DataLayout& DL
const llvm::TargetLoweringBase::AddrMode& AM
llvm::Type* Ty
unsigned int AS = 0

Sched::Preference getSchedulingPreference() const

Description

Return target scheduling preference.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:694

virtual Sched::Preference getSchedulingPreference(
    llvm::SDNode*) const

Description

Some scheduler, e.g. hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:701

Parameters

llvm::SDNode* 

virtual llvm::EVT getSetCCResultType(
    const llvm::DataLayout& DL,
    llvm::LLVMContext& Context,
    llvm::EVT VT) const

Description

Return the ValueType of the result of SETCC operations.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:661

Parameters

const llvm::DataLayout& DL
llvm::LLVMContext& Context
llvm::EVT VT

llvm::EVT getShiftAmountTy(
    llvm::EVT LHSTy,
    const llvm::DataLayout& DL,
    bool LegalTypes = true) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:277

Parameters

llvm::EVT LHSTy
const llvm::DataLayout& DL
bool LegalTypes = true

llvm::MVT getSimpleValueType(
    const llvm::DataLayout& DL,
    llvm::Type* Ty,
    bool AllowUnknown = false) const

Description

Return the MVT corresponding to this LLVM type. See getValueType.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1266

Parameters

const llvm::DataLayout& DL
llvm::Type* Ty
bool AllowUnknown = false

int getSqrtRefinementSteps(
    llvm::EVT VT,
    llvm::MachineFunction& MF) const

Description

Return the refinement step count for a square root of the given type based on the function's attributes. If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:375

Parameters

llvm::EVT VT
llvm::MachineFunction& MF

unsigned int
getStackPointerRegisterToSaveRestore() const

Description

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1559

virtual llvm::StringRef getStackProbeSymbolName(
    llvm::MachineFunction& MF) const

Description

Returns the name of the symbol used to emit stack probes or the empty string if not applicable.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1642

Parameters

llvm::MachineFunction& MF

llvm::TargetLoweringBase::LegalizeAction
getStrictFPOperationAction(unsigned int Op,
                           llvm::EVT VT) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:949

Parameters

unsigned int Op
llvm::EVT VT

const llvm::TargetMachine& getTargetMachine()
    const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:243

virtual bool getTgtMemIntrinsic(
    llvm::TargetLoweringBase::IntrinsicInfo&,
    const llvm::CallInst&,
    llvm::MachineFunction&,
    unsigned int) const

Description

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:863

Parameters

llvm::TargetLoweringBase::IntrinsicInfo&
const llvm::CallInst&
llvm::MachineFunction&
unsigned int 

llvm::TargetLoweringBase::LegalizeAction
getTruncStoreAction(llvm::EVT ValVT,
                    llvm::EVT MemVT) const

Description

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1090

Parameters

llvm::EVT ValVT
llvm::EVT MemVT

llvm::TargetLoweringBase::LegalizeTypeAction
getTypeAction(llvm::MVT VT) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:787

Parameters

llvm::MVT VT

llvm::TargetLoweringBase::LegalizeTypeAction
getTypeAction(llvm::LLVMContext& Context,
              llvm::EVT VT) const

Description

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:784

Parameters

llvm::LLVMContext& Context
llvm::EVT VT

std::pair<int, MVT> getTypeLegalizationCost(
    const llvm::DataLayout& DL,
    llvm::Type* Ty) const

Description

Estimate the cost of type-legalization and the legalized type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1675

Parameters

const llvm::DataLayout& DL
llvm::Type* Ty

llvm::EVT getTypeToExpandTo(
    llvm::LLVMContext& Context,
    llvm::EVT VT) const

Description

For types supported by the target, this is an identity function. For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:805

Parameters

llvm::LLVMContext& Context
llvm::EVT VT

llvm::MVT getTypeToPromoteTo(unsigned int Op,
                             llvm::MVT VT) const

Description

If the action for this operation is to promote, this method returns the ValueType to promote to.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1199

Parameters

unsigned int Op
llvm::MVT VT

llvm::EVT getTypeToTransformTo(
    llvm::LLVMContext& Context,
    llvm::EVT VT) const

Description

For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:797

Parameters

llvm::LLVMContext& Context
llvm::EVT VT

virtual unsigned int getVaListSizeInBits(
    const llvm::DataLayout& DL) const

Description

Returns the size of the platform's va_list object.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1391

Parameters

const llvm::DataLayout& DL

llvm::EVT getValueType(
    const llvm::DataLayout& DL,
    llvm::Type* Ty,
    bool AllowUnknown = false) const

Description

Return the EVT corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1226

Parameters

const llvm::DataLayout& DL
llvm::Type* Ty
bool AllowUnknown = false

const llvm::TargetLoweringBase::
    ValueTypeActionImpl&
    getValueTypeActions() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:776

virtual llvm::MVT getVectorIdxTy(
    const llvm::DataLayout& DL) const

Description

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:283

Parameters

const llvm::DataLayout& DL

unsigned int getVectorTypeBreakdown(
    llvm::LLVMContext& Context,
    llvm::EVT VT,
    llvm::EVT& IntermediateVT,
    unsigned int& NumIntermediates,
    llvm::MVT& RegisterVT) const

Description

Vector types are broken down into some number of legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:828

Parameters

llvm::LLVMContext& Context
llvm::EVT VT
llvm::EVT& IntermediateVT
unsigned int& NumIntermediates
llvm::MVT& RegisterVT

virtual unsigned int
getVectorTypeBreakdownForCallingConv(
    llvm::LLVMContext& Context,
    CallingConv::ID CC,
    llvm::EVT VT,
    llvm::EVT& IntermediateVT,
    unsigned int& NumIntermediates,
    llvm::MVT& RegisterVT) const

Description

Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. This occurs even if the vector type is legal.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:836

Parameters

llvm::LLVMContext& Context
CallingConv::ID CC
llvm::EVT VT
llvm::EVT& IntermediateVT
unsigned int& NumIntermediates
llvm::MVT& RegisterVT

virtual bool hasAndNot(llvm::SDValue X) const

Description

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:548

Parameters

llvm::SDValue X

virtual bool hasAndNotCompare(
    llvm::SDValue Y) const

Description

Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) != Y ---> (~X & Y) != 0 This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant. Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 ---> (X & 8) != 0

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:541

Parameters

llvm::SDValue Y

bool hasBigEndianPartOrdering(
    llvm::EVT VT,
    const llvm::DataLayout& DL) const

Description

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1375

Parameters

llvm::EVT VT
const llvm::DataLayout& DL

virtual bool hasBitPreservingFPLogic(
    llvm::EVT VT) const

Description

Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:487

Parameters

llvm::EVT VT

virtual bool hasBitTest(llvm::SDValue X,
                        llvm::SDValue Y) const

Description

Return true if the target has a bit-test instruction: (X & (1 < < Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:558

Parameters

llvm::SDValue X
llvm::SDValue Y

bool hasExtractBitsInsn() const

Description

Return true if the target has BitExtract instructions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:305

virtual llvm::MVT hasFastEqualityCompare(
    unsigned int NumBits) const

Description

Return the preferred operand type if the target has a quick way to compare integer values of the given size. Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:524

Parameters

unsigned int NumBits

bool hasMultipleConditionRegisters() const

Description

Return true if multiple condition registers are available.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:300

virtual bool hasPairedLoad(llvm::EVT,
                           unsigned int&) const

Description

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load. This information is *not* used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32). In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2429

Parameters

llvm::EVT
unsigned int& 

virtual bool hasStandaloneRem(llvm::EVT VT) const

Description

Return true if the target can handle a standalone remainder operation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:342

Parameters

llvm::EVT VT

bool hasTargetDAGCombine(ISD::NodeType NT) const

Description

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1381

Parameters

ISD::NodeType NT

virtual bool hasVectorBlend() const

Description

Return true if the target has a vector blend instruction.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2435

void initActions()

Description

Initialize all of the actions to default values.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:240

virtual void insertSSPDeclarations(
    llvm::Module& M) const

Description

Inserts necessary declarations for SSP (stack protection) purpose. Should be used only when getIRStackGuard returns nullptr.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1613

Parameters

llvm::Module& M

virtual bool isBinOp(unsigned int Opcode) const

Description

Return true if the node is a math/logic binary operator.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2271

Parameters

unsigned int Opcode

virtual bool isCheapToSpeculateCtlz() const

Description

Return true if it is cheap to speculate a call to intrinsic ctlz.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:470

virtual bool isCheapToSpeculateCttz() const

Description

Return true if it is cheap to speculate a call to intrinsic cttz.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:465

virtual bool isCommutativeBinOp(
    unsigned int Opcode) const

Description

Returns true if the opcode is a commutative binary operation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2235

Parameters

unsigned int Opcode

bool isCondCodeLegal(ISD::CondCode CC,
                     llvm::MVT VT) const

Description

Return true if the specified condition code is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1186

Parameters

ISD::CondCode CC
llvm::MVT VT

bool isCondCodeLegalOrCustom(ISD::CondCode CC,
                             llvm::MVT VT) const

Description

Return true if the specified condition code is legal or custom on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1192

Parameters

ISD::CondCode CC
llvm::MVT VT

virtual bool isCtlzFast() const

Description

Return true if ctlz instruction is fast.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:475

virtual bool isEqualityCmpFoldedWithSignedCmp()
    const

Description

Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:481

bool isExtFree(const llvm::Instruction* I) const

Description

Return true if the extension represented by \p I is free. Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided by \p I to decide whether or not \p I is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2326

Parameters

const llvm::Instruction* I

virtual bool isExtFreeImpl(
    const llvm::Instruction* I) const

Description

Return true if the extension represented by \p I is free.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2846

Parameters

const llvm::Instruction* I

bool isExtLoad(const llvm::LoadInst* Load,
               const llvm::Instruction* Ext,
               const llvm::DataLayout& DL) const

Description

Return true if \p Load and \p Ext can form an ExtLoad. For example, in AArch64 %L = load i8, i8* %ptr %E = zext i8 %L to i32 can be lowered into one load instruction ldrb w0, [x0]

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2351

Parameters

const llvm::LoadInst* Load
const llvm::Instruction* Ext
const llvm::DataLayout& DL

virtual bool isExtractSubvectorCheap(
    llvm::EVT ResVT,
    llvm::EVT SrcVT,
    unsigned int Index) const

Description

Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2557

Parameters

llvm::EVT ResVT
llvm::EVT SrcVT
unsigned int Index

virtual bool isExtractVecEltCheap(
    llvm::EVT VT,
    unsigned int Index) const

Description

Return true if extraction of a scalar element from the given vector type at the given index is cheap. For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2572

Parameters

llvm::EVT VT
unsigned int Index

virtual bool isFAbsFree(llvm::EVT VT) const

Description

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2505

Parameters

llvm::EVT VT

virtual bool isFMADLegalForFAddFSub(
    const llvm::SelectionDAG& DAG,
    const llvm::SDNode* N) const

Description

Returns true if the FADD or FSUB node passed could legally be combined with an fmul to form an ISD::FMAD.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2530

Parameters

const llvm::SelectionDAG& DAG
const llvm::SDNode* N

virtual bool isFMAFasterThanFMulAndFAdd(
    const llvm::Function& F,
    llvm::Type*) const

Description

IR version

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2524

Parameters

const llvm::Function& F
llvm::Type* 

virtual bool isFMAFasterThanFMulAndFAdd(
    const llvm::MachineFunction& MF,
    llvm::EVT) const

Description

Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd. NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2518

Parameters

const llvm::MachineFunction& MF
llvm::EVT 

virtual bool isFNegFree(llvm::EVT VT) const

Description

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2498

Parameters

llvm::EVT VT

virtual bool isFPExtFoldable(
    const llvm::SelectionDAG& DAG,
    unsigned int Opcode,
    llvm::EVT DestVT,
    llvm::EVT SrcVT) const

Description

Return true if an fpext operation input to an \p Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2485

Parameters

const llvm::SelectionDAG& DAG
unsigned int Opcode
llvm::EVT DestVT
llvm::EVT SrcVT

virtual bool isFPExtFree(llvm::EVT DestVT,
                         llvm::EVT SrcVT) const

Description

Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2476

Parameters

llvm::EVT DestVT
llvm::EVT SrcVT

virtual bool isFPImmLegal(
    const llvm::APFloat&,
    llvm::EVT,
    bool ForCodeSize = false) const

Description

Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:872

Parameters

const llvm::APFloat&
llvm::EVT
bool ForCodeSize = false

virtual bool isFreeAddrSpaceCast(
    unsigned int SrcAS,
    unsigned int DestAS) const

Description

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we are happy to sink it into basic blocks. A cast may be free, but not necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1654

Parameters

unsigned int SrcAS
unsigned int DestAS

virtual bool isFsqrtCheap(
    llvm::SDValue X,
    llvm::SelectionDAG& DAG) const

Description

Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:347

Parameters

llvm::SDValue X
llvm::SelectionDAG& DAG

bool isIndexedLoadLegal(unsigned int IdxMode,
                        llvm::EVT VT) const

Description

Return true if the specified indexed load is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1121

Parameters

unsigned int IdxMode
llvm::EVT VT

bool isIndexedMaskedLoadLegal(
    unsigned int IdxMode,
    llvm::EVT VT) const

Description

Return true if the specified indexed load is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1149

Parameters

unsigned int IdxMode
llvm::EVT VT

bool isIndexedMaskedStoreLegal(
    unsigned int IdxMode,
    llvm::EVT VT) const

Description

Return true if the specified indexed load is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1163

Parameters

unsigned int IdxMode
llvm::EVT VT

bool isIndexedStoreLegal(unsigned int IdxMode,
                         llvm::EVT VT) const

Description

Return true if the specified indexed load is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1135

Parameters

unsigned int IdxMode
llvm::EVT VT

virtual bool isIntDivCheap(
    llvm::EVT VT,
    llvm::AttributeList Attr) const

Description

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. The definition of "cheaper" may depend on whether we're optimizing for speed or for size.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:339

Parameters

llvm::EVT VT
llvm::AttributeList Attr

bool isJumpExpensive() const

Description

Return true if Flow Control is an expensive operation that should be avoided.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:394

virtual bool isJumpTableRelative() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1553

virtual bool isLegalAddImmediate(int64_t) const

Description

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2214

Parameters

int64_t 

virtual bool isLegalAddressingMode(
    const llvm::DataLayout& DL,
    const llvm::TargetLoweringBase::AddrMode& AM,
    llvm::Type* Ty,
    unsigned int AddrSpace,
    llvm::Instruction* I = nullptr) const

Description

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well. If the address space cannot be determined, it will be -1. TODO: Remove default argument

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2185

Parameters

const llvm::DataLayout& DL
const llvm::TargetLoweringBase::AddrMode& AM
llvm::Type* Ty
unsigned int AddrSpace
llvm::Instruction* I = nullptr

virtual bool isLegalICmpImmediate(int64_t) const

Description

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2207

Parameters

int64_t 

bool isLegalRC(
    const llvm::TargetRegisterInfo& TRI,
    const llvm::TargetRegisterClass& RC) const

Description

Return true if the value types that can be represented by the specified register class are all legal.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2927

Parameters

const llvm::TargetRegisterInfo& TRI
const llvm::TargetRegisterClass& RC

virtual bool isLegalStoreImmediate(
    int64_t Value) const

Description

Return true if the specified immediate is legal for the value input of a store instruction.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2220

Parameters

int64_t Value

virtual bool isLoadBitCastBeneficial(
    llvm::EVT LoadVT,
    llvm::EVT BitcastVT,
    const llvm::SelectionDAG& DAG,
    const llvm::MachineMemOperand& MMO) const

Description

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:412

Parameters

llvm::EVT LoadVT
llvm::EVT BitcastVT
const llvm::SelectionDAG& DAG
const llvm::MachineMemOperand& MMO

bool isLoadExtLegal(unsigned int ExtType,
                    llvm::EVT ValVT,
                    llvm::EVT MemVT) const

Description

Return true if the specified load with extension is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1076

Parameters

unsigned int ExtType
llvm::EVT ValVT
llvm::EVT MemVT

bool isLoadExtLegalOrCustom(unsigned int ExtType,
                            llvm::EVT ValVT,
                            llvm::EVT MemVT) const

Description

Return true if the specified load with extension is legal or custom on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1082

Parameters

unsigned int ExtType
llvm::EVT ValVT
llvm::EVT MemVT

virtual bool isMaskAndCmp0FoldingBeneficial(
    const llvm::Instruction& AndI) const

Description

Return if the target supports combining a chain like: into a single machine instruction of a form like:

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:507

Parameters

const llvm::Instruction& AndI

virtual bool isMultiStoresCheaperThanBitsMerge(
    llvm::EVT LTy,
    llvm::EVT HTy) const

Description

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:493

Parameters

llvm::EVT LTy
llvm::EVT HTy

virtual bool isNarrowingProfitable(
    llvm::EVT,
    llvm::EVT) const

Description

Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2539

Parameters

llvm::EVT
llvm::EVT 

virtual bool isNoopAddrSpaceCast(
    unsigned int SrcAS,
    unsigned int DestAS) const

Description

Returns true if a cast between SrcAS and DestAS is a noop.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1647

Parameters

unsigned int SrcAS
unsigned int DestAS

bool isOperationCustom(unsigned int Op,
                       llvm::EVT VT) const

Description

Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:993

Parameters

unsigned int Op
llvm::EVT VT

bool isOperationExpand(unsigned int Op,
                       llvm::EVT VT) const

Description

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1051

Parameters

unsigned int Op
llvm::EVT VT

bool isOperationLegal(unsigned int Op,
                      llvm::EVT VT) const

Description

Return true if the specified operation is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1056

Parameters

unsigned int Op
llvm::EVT VT

bool isOperationLegalOrCustom(unsigned int Op,
                              llvm::EVT VT) const

Description

Return true if the specified operation is legal on this target or can be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:966

Parameters

unsigned int Op
llvm::EVT VT

bool isOperationLegalOrCustomOrPromote(
    unsigned int Op,
    llvm::EVT VT) const

Description

Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. This is used to help guide high-level lowering decisions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:984

Parameters

unsigned int Op
llvm::EVT VT

bool isOperationLegalOrPromote(unsigned int Op,
                               llvm::EVT VT) const

Description

Return true if the specified operation is legal on this target or can be made legal using promotion. This is used to help guide high-level lowering decisions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:975

Parameters

unsigned int Op
llvm::EVT VT

bool isPredictableSelectExpensive() const

Description

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:398

virtual bool isProfitableToCombineMinNumMaxNum(
    llvm::EVT VT) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1884

Parameters

llvm::EVT VT

virtual bool isProfitableToHoist(
    llvm::Instruction* I) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2315

Parameters

llvm::Instruction* I

virtual bool isSExtCheaperThanZExt(
    llvm::EVT FromTy,
    llvm::EVT ToTy) const

Description

Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2394

Parameters

llvm::EVT FromTy
llvm::EVT ToTy

virtual bool isSafeMemOpType(llvm::MVT) const

Description

Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1541

Parameters

llvm::MVT 

virtual bool isSelectSupported(
    llvm::TargetLoweringBase::SelectSupportKind)
    const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:287

Parameters

llvm::TargetLoweringBase::SelectSupportKind 

virtual bool isShuffleMaskLegal(ArrayRef<int>,
                                llvm::EVT) const

Description

Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:881

Parameters

ArrayRef<int>
llvm::EVT 

bool isSlowDivBypassed() const

Description

Returns true if target has indicated at least one type should be bypassed.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:384

virtual bool isStoreBitCastBeneficial(
    llvm::EVT StoreVT,
    llvm::EVT BitcastVT,
    const llvm::SelectionDAG& DAG,
    const llvm::MachineMemOperand& MMO) const

Description

Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:435

Parameters

llvm::EVT StoreVT
llvm::EVT BitcastVT
const llvm::SelectionDAG& DAG
const llvm::MachineMemOperand& MMO

bool isStrictFPEnabled() const

Description

Return true if the target support strict float operation

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:234

bool isSuitableForBitTests(
    unsigned int NumDests,
    unsigned int NumCmps,
    const llvm::APInt& Low,
    const llvm::APInt& High,
    const llvm::DataLayout& DL) const

Description

Return true if lowering to a bit test is suitable for a set of case clusters which contains \p NumDests unique destinations, \p Low and\p High as its lowest and highest case values, and expects \p NumCmps case value comparisons. Check if the number of destinations, comparison metric, and range are all suitable.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1026

Parameters

unsigned int NumDests
unsigned int NumCmps
const llvm::APInt& Low
const llvm::APInt& High
const llvm::DataLayout& DL

virtual bool isSuitableForJumpTable(
    const llvm::SwitchInst* SI,
    uint64_t NumCases,
    uint64_t Range,
    llvm::ProfileSummaryInfo* PSI,
    llvm::BlockFrequencyInfo* BFI) const

Description

Return true if lowering to a jump table is suitable for a set of case clusters which may contain \p NumCases cases, \p Range range of values.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1017

Parameters

const llvm::SwitchInst* SI
uint64_t NumCases
uint64_t Range
llvm::ProfileSummaryInfo* PSI
llvm::BlockFrequencyInfo* BFI

virtual bool isSupportedFixedPointOperation(
    unsigned int Op,
    llvm::EVT VT,
    unsigned int Scale) const

Description

Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. If not, the operation is illegal.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:913

Parameters

unsigned int Op
llvm::EVT VT
unsigned int Scale

bool isTruncStoreLegal(llvm::EVT ValVT,
                       llvm::EVT MemVT) const

Description

Return true if the specified store with truncation is legal on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1101

Parameters

llvm::EVT ValVT
llvm::EVT MemVT

bool isTruncStoreLegalOrCustom(
    llvm::EVT ValVT,
    llvm::EVT MemVT) const

Description

Return true if the specified store with truncation has solution on this target.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1107

Parameters

llvm::EVT ValVT
llvm::EVT MemVT

virtual bool isTruncateFree(llvm::EVT FromVT,
                            llvm::EVT ToVT) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2311

Parameters

llvm::EVT FromVT
llvm::EVT ToVT

virtual bool isTruncateFree(
    llvm::Type* FromTy,
    llvm::Type* ToTy) const

Description

Return true if it's free to truncate a value of type FromTy to type ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy < = ToTy.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2298

Parameters

llvm::Type* FromTy
llvm::Type* ToTy

bool isTypeLegal(llvm::EVT VT) const

Description

Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:750

Parameters

llvm::EVT VT

virtual bool isVectorClearMaskLegal(
    ArrayRef<int>,
    llvm::EVT) const

Description

Similar to isShuffleMaskLegal. Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:894

Parameters

ArrayRef<int>
llvm::EVT 

virtual bool isVectorLoadExtDesirable(
    llvm::SDValue ExtVal) const

Description

Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2494

Parameters

llvm::SDValue ExtVal

virtual bool isVectorShiftByScalarCheap(
    llvm::Type* Ty) const

Description

Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount which will vary across each lane. On x86, for example, there is a "psllw" instruction for the former case, but no simple instruction for a general "a << b" operation on vectors.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2230

Parameters

llvm::Type* Ty

virtual bool isZExtFree(llvm::SDValue Val,
                        llvm::EVT VT2) const

Description

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2469

Parameters

llvm::SDValue Val
llvm::EVT VT2

virtual bool isZExtFree(llvm::Type* FromTy,
                        llvm::Type* ToTy) const

Description

Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2384

Parameters

llvm::Type* FromTy
llvm::Type* ToTy

virtual bool isZExtFree(llvm::EVT FromTy,
                        llvm::EVT ToTy) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2388

Parameters

llvm::EVT FromTy
llvm::EVT ToTy

virtual llvm::LoadInst*
lowerIdempotentRMWIntoFencedLoad(
    llvm::AtomicRMWInst* RMWI) const

Description

On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1854

Parameters

llvm::AtomicRMWInst* RMWI

virtual bool lowerInterleavedLoad(
    llvm::LoadInst* LI,
    ArrayRef<llvm::ShuffleVectorInst*> Shuffles,
    ArrayRef<unsigned int> Indices,
    unsigned int Factor) const

Description

Lower an interleaved load to target specific intrinsics. Return true on success. \p LI is the vector load instruction.\p Shuffles is the shufflevector list to DE-interleave the loaded vector.\p Indices is the corresponding indices for each shufflevector.\p Factor is the interleave factor.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2448

Parameters

llvm::LoadInst* LI
ArrayRef<llvm::ShuffleVectorInst*> Shuffles
ArrayRef<unsigned int> Indices
unsigned int Factor

virtual bool lowerInterleavedStore(
    llvm::StoreInst* SI,
    llvm::ShuffleVectorInst* SVI,
    unsigned int Factor) const

Description

Lower an interleaved store to target specific intrinsics. Return true on success. \p SI is the vector store instruction.\p SVI is the shufflevector to RE-interleave the stored vector.\p Factor is the interleave factor.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2461

Parameters

llvm::StoreInst* SI
llvm::ShuffleVectorInst* SVI
unsigned int Factor

virtual void markLibCallAttributes(
    llvm::MachineFunction* MF,
    unsigned int CC,
    int& Args) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:210

Parameters

llvm::MachineFunction* MF
unsigned int CC
int& Args

virtual bool mergeStoresAfterLegalization(
    llvm::EVT MemVT) const

Description

Allow store merging for the specified type after legalization in addition to before legalization. This may transform stores that do not exist earlier (for example, stores created from intrinsics).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:454

Parameters

llvm::EVT MemVT

virtual bool needsFixedCatchObjects() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1579

virtual bool preferIncOfAddToSubOfNot(
    llvm::EVT VT) const

Description

These two forms are equivalent: sub %y, (xor %x, -1) add (add %x, 1), %y The variant with two add's is IR-canonical. Some targets may prefer one to the other.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:629

Parameters

llvm::EVT VT

bool rangeFitsInWord(
    const llvm::APInt& Low,
    const llvm::APInt& High,
    const llvm::DataLayout& DL) const

Description

Check whether the range [Low,High] fits in a machine word.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1007

Parameters

const llvm::APInt& Low
const llvm::APInt& High
const llvm::DataLayout& DL

virtual bool reduceSelectOfFPConstantLoads(
    llvm::EVT CmpOpVT) const

Description

Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. The parameter may be used to differentiate a select with FP compare from integer compare.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:295

Parameters

llvm::EVT CmpOpVT

virtual bool requiresUniformRegister(
    llvm::MachineFunction& MF,
    const llvm::Value*) const

Description

Allows target to decide about the register class of the specific value that is live outside the defining block. Returns true if the value needs uniform register class.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:717

Parameters

llvm::MachineFunction& MF
const llvm::Value* 

void setBooleanContents(
    llvm::TargetLoweringBase::BooleanContent Ty)

Description

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1920

Parameters

llvm::TargetLoweringBase::BooleanContent Ty

void setBooleanContents(
    llvm::TargetLoweringBase::BooleanContent
        IntTy,
    llvm::TargetLoweringBase::BooleanContent
        FloatTy)

Description

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1927

Parameters

llvm::TargetLoweringBase::BooleanContent IntTy
llvm::TargetLoweringBase::BooleanContent FloatTy

void setBooleanVectorContents(
    llvm::TargetLoweringBase::BooleanContent Ty)

Description

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1934

Parameters

llvm::TargetLoweringBase::BooleanContent Ty

void setCmpLibcallCC(RTLIB::Libcall Call,
                     ISD::CondCode CC)

Description

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2626

Parameters

RTLIB::Libcall Call
ISD::CondCode CC

void setCondCodeAction(
    ISD::CondCode CC,
    llvm::MVT VT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2069

Parameters

ISD::CondCode CC
llvm::MVT VT
llvm::TargetLoweringBase::LegalizeAction Action

void setHasExtractBitsInsn(
    bool hasExtractInsn = true)

Description

Tells the code generator that the target has BitExtract instructions. The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1969

Parameters

bool hasExtractInsn = true

void setHasMultipleConditionRegisters(
    bool hasManyRegs = true)

Description

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1961

Parameters

bool hasManyRegs = true

void setIndexedLoadAction(
    unsigned int IdxMode,
    llvm::MVT VT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2034

Parameters

unsigned int IdxMode
llvm::MVT VT
llvm::TargetLoweringBase::LegalizeAction Action

void setIndexedMaskedLoadAction(
    unsigned int IdxMode,
    llvm::MVT VT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it. NOTE: All indexed mode masked loads are initialized to Expand in TargetLowering.cpp

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2052

Parameters

unsigned int IdxMode
llvm::MVT VT
llvm::TargetLoweringBase::LegalizeAction Action

void setIndexedMaskedStoreAction(
    unsigned int IdxMode,
    llvm::MVT VT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it. NOTE: All indexed mode masked stores are initialized to Expand in TargetLowering.cpp

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2062

Parameters

unsigned int IdxMode
llvm::MVT VT
llvm::TargetLoweringBase::LegalizeAction Action

void setIndexedStoreAction(
    unsigned int IdxMode,
    llvm::MVT VT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2043

Parameters

unsigned int IdxMode
llvm::MVT VT
llvm::TargetLoweringBase::LegalizeAction Action

void setJumpIsExpensive(bool isExpensive = true)

Description

Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1976

Parameters

bool isExpensive = true

void setLibcallCallingConv(RTLIB::Libcall Call,
                           CallingConv::ID CC)

Description

Set the CallingConv that should be used for the specified libcall.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2637

Parameters

RTLIB::Libcall Call
CallingConv::ID CC

void setLibcallName(RTLIB::Libcall Call,
                    const char* Name)

Description

Rename the default libcall routine name for the specified libcall.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2615

Parameters

RTLIB::Libcall Call
const char* Name

void setLoadExtAction(
    unsigned int ExtType,
    llvm::MVT ValVT,
    llvm::MVT MemVT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2011

Parameters

unsigned int ExtType
llvm::MVT ValVT
llvm::MVT MemVT
llvm::TargetLoweringBase::LegalizeAction Action

void setMaxAtomicSizeInBitsSupported(
    unsigned int SizeInBits)

Description

Set the maximum atomic operation size supported by the backend. Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded by AtomicExpandPass into an __atomic_* library call.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2130

Parameters

unsigned int SizeInBits

void setMaximumJumpTableSize(unsigned int)

Description

Indicate the maximum number of entries in jump tables. Set to zero to generate unlimited jump tables.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1948

Parameters

unsigned int 

void setMinCmpXchgSizeInBits(
    unsigned int SizeInBits)

Description

Sets the minimum cmpxchg or ll/sc size supported by the backend.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2135

Parameters

unsigned int SizeInBits

void setMinFunctionAlignment(
    llvm::Align Alignment)

Description

Set the target's minimum function alignment.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2106

Parameters

llvm::Align Alignment

void setMinStackArgumentAlignment(
    llvm::Align Alignment)

Description

Set the minimum stack alignment of an argument.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2122

Parameters

llvm::Align Alignment

void setMinimumJumpTableEntries(unsigned int Val)

Description

Indicate the minimum number of blocks to generate jump tables.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1944

Parameters

unsigned int Val

void setOperationAction(
    unsigned int Op,
    llvm::MVT VT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified operation does not work with the specified type and indicate what to do about it. Note that VT may refer to either the type of a result or that of an operand of Op.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2003

Parameters

unsigned int Op
llvm::MVT VT
llvm::TargetLoweringBase::LegalizeAction Action

void setOperationPromotedToType(unsigned int Opc,
                                llvm::MVT OrigVT,
                                llvm::MVT DestVT)

Description

Convenience method to set an operation to Promote and specify the type in a single call.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2092

Parameters

unsigned int Opc
llvm::MVT OrigVT
llvm::MVT DestVT

void setPrefFunctionAlignment(
    llvm::Align Alignment)

Description

Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2112

Parameters

llvm::Align Alignment

void setPrefLoopAlignment(llvm::Align Alignment)

Description

Set the target's preferred loop alignment. Default alignment is one, it means the target does not care about loop alignment. The target may also override getPrefLoopAlignment to provide per-loop values.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2119

Parameters

llvm::Align Alignment

void setSchedulingPreference(
    Sched::Preference Pref)

Description

Specify the target scheduling preference.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1939

Parameters

Sched::Preference Pref

void setStackPointerRegisterToSaveRestore(
    unsigned int R)

Description

If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1952

Parameters

unsigned int R

void setSupportsUnalignedAtomics(
    bool UnalignedSupported)

Description

Sets whether unaligned atomic operations are supported.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2140

Parameters

bool UnalignedSupported

void setTargetDAGCombine(ISD::NodeType NT)

Description

Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2100

Parameters

ISD::NodeType NT

void setTruncStoreAction(
    llvm::MVT ValVT,
    llvm::MVT MemVT,
    llvm::TargetLoweringBase::LegalizeAction
        Action)

Description

Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2023

Parameters

llvm::MVT ValVT
llvm::MVT MemVT
llvm::TargetLoweringBase::LegalizeAction Action

virtual bool shouldAlignPointerArgs(
    llvm::CallInst*,
    unsigned int&,
    unsigned int&) const

Description

Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1662

Parameters

llvm::CallInst*
unsigned int&
unsigned int& 

virtual bool shouldAvoidTransformToShift(
    llvm::EVT VT,
    unsigned int Amount) const

Description

Return true if creating a shift of the type by the given amount is not profitable.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2606

Parameters

llvm::EVT VT
unsigned int Amount

virtual bool shouldConsiderGEPOffsetSplit() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2602

virtual bool shouldConvertConstantLoadToIntImm(
    const llvm::APInt& Imm,
    llvm::Type* Ty) const

Description

Return true if it is beneficial to convert a load of a constant to just the constant itself. On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2548

Parameters

const llvm::APInt& Imm
llvm::Type* Ty

virtual llvm::TargetLoweringBase::
    AtomicExpansionKind
    shouldExpandAtomicCmpXchgInIR(
        llvm::AtomicCmpXchgInst* AI) const

Description

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1831

Parameters

llvm::AtomicCmpXchgInst* AI

virtual llvm::TargetLoweringBase::
    AtomicExpansionKind
    shouldExpandAtomicLoadInIR(
        llvm::LoadInst* LI) const

Description

Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1824

Parameters

llvm::LoadInst* LI

virtual llvm::TargetLoweringBase::
    AtomicExpansionKind
    shouldExpandAtomicRMWInIR(
        llvm::AtomicRMWInst* RMW) const

Description

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. Default is to never expand.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1837

Parameters

llvm::AtomicRMWInst* RMW

virtual bool shouldExpandAtomicStoreInIR(
    llvm::StoreInst* SI) const

Description

Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1808

Parameters

llvm::StoreInst* SI

virtual bool shouldExpandBuildVectorWithShuffles(
    llvm::EVT,
    unsigned int DefinedValues) const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:330

Parameters

llvm::EVT
unsigned int DefinedValues

virtual bool shouldExpandShift(
    llvm::SelectionDAG& DAG,
    llvm::SDNode* N) const

Description

Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a library call is preferred (e.g for code-size reasons).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:743

Parameters

llvm::SelectionDAG& DAG
llvm::SDNode* N

virtual bool shouldExtendTypeInLibCall(
    llvm::EVT Type) const

Description

Returns true if arguments should be extended in lib calls.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1818

Parameters

llvm::EVT Type

virtual bool shouldFoldConstantShiftPairToMask(
    const llvm::SDNode* N,
    llvm::CombineLevel Level) const

Description

Return true if it is profitable to fold a pair of shifts into a mask. This is usually true on most targets. But some targets, like Thumb1, have immediate shift instructions, but no immediate "and" instruction; this makes the fold unprofitable.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:574

Parameters

const llvm::SDNode* N
llvm::CombineLevel Level

virtual bool shouldFoldMaskToVariableShiftPair(
    llvm::SDValue X) const

Description

There are two ways to clear extreme bits (either low or high): Mask: x & (-1 < < y) (the instcombine canonical form) Shifts: x >> y < < y Return true if the variant with 2 variable shifts is preferred. Return false if there is no preference.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:565

Parameters

llvm::SDValue X

virtual bool shouldFormOverflowOp(
    unsigned int Opcode,
    llvm::EVT VT) const

Description

Try to convert math with an overflow comparison into the corresponding DAG node operation. Targets may want to override this independently of whether the operation is legal/custom for the given type because it may obscure matching of other patterns.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2580

Parameters

unsigned int Opcode
llvm::EVT VT

virtual bool shouldInsertFencesForAtomic(
    const llvm::Instruction* I) const

Description

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic. This should be true for most architectures with weak memory ordering. Defaults to false.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1707

Parameters

const llvm::Instruction* I

virtual bool shouldNormalizeToSelectSequence(
    llvm::LLVMContext& Context,
    llvm::EVT VT) const

Description

Returns true if we should normalize select(N0 &N 1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. Targets that are able to perform and/or on flags should return false here.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1871

Parameters

llvm::LLVMContext& Context
llvm::EVT VT

virtual bool
shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
    llvm::SDValue X,
    llvm::ConstantSDNode* XC,
    llvm::ConstantSDNode* CC,
    llvm::SDValue Y,
    unsigned int OldShiftOpcode,
    unsigned int NewShiftOpcode,
    llvm::SelectionDAG& DAG) const

Description

Given the pattern (X & (C l>>/ < < Y)) ==/!= 0 return true if it should be transformed into: ((X < </l >> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:599

Parameters

llvm::SDValue X
llvm::ConstantSDNode* XC
llvm::ConstantSDNode* CC
llvm::SDValue Y
unsigned int OldShiftOpcode
unsigned int NewShiftOpcode
llvm::SelectionDAG& DAG

virtual bool shouldReduceLoadWidth(
    llvm::SDNode* Load,
    ISD::LoadExtType ExtTy,
    llvm::EVT NewVT) const

Description

Return true if it is profitable to reduce a load to a smaller type. Example: (i16 (trunc (i32 (load x))) -> i16 load x

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1362

Parameters

llvm::SDNode* Load
ISD::LoadExtType ExtTy
llvm::EVT NewVT

virtual bool shouldScalarizeBinop(
    llvm::SDValue VecOp) const

Description

Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2564

Parameters

llvm::SDValue VecOp

virtual bool shouldSignExtendTypeInLibCall(
    llvm::EVT Type,
    bool IsSigned) const

Description

Returns true if arguments should be sign-extended in lib calls.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1813

Parameters

llvm::EVT Type
bool IsSigned

virtual bool shouldSinkOperands(
    llvm::Instruction* I,
    SmallVectorImpl<llvm::Use*>& Ops) const

Description

Return true if sinking I's operands to the same basic block as I is profitable, e.g. because the operands can be folded into a target instruction during instruction selection. After calling the function\p Ops contains the Uses to sink ordered by dominance (dominating users come first).

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:2403

Parameters

llvm::Instruction* I
SmallVectorImpl<llvm::Use*>& Ops

virtual bool shouldSplatInsEltVarIndex(
    llvm::EVT) const

Description

Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:649

Parameters

llvm::EVT 

virtual bool shouldTransformSignedTruncationCheck(
    llvm::EVT XVT,
    unsigned int KeptBits) const

Description

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add %x, (1 < < (KeptBits-1))) srccond (1 < < KeptBits) Into it's more traditional form: ((%x < < C) a>> C) dstcond %x Return true if we should transform. Return false if there is no preference.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:586

Parameters

llvm::EVT XVT
unsigned int KeptBits

virtual bool shouldUseStrictFP_TO_INT(
    llvm::EVT FpVT,
    llvm::EVT IntVT,
    bool IsSigned) const

Description

Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. This may be true if the target throws exceptions for out of bounds conversions or has fast FP CMOV.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1908

Parameters

llvm::EVT FpVT
llvm::EVT IntVT
bool IsSigned

virtual bool storeOfVectorConstantIsCheap(
    llvm::EVT MemVT,
    unsigned int NumElem,
    unsigned int AddrSpace) const

Description

Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:445

Parameters

llvm::EVT MemVT
unsigned int NumElem
unsigned int AddrSpace

bool supportsUnalignedAtomics() const

Description

Whether the target supports unaligned atomic operations.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1702

virtual bool useSoftFloat() const

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:245

virtual bool useStackGuardXorFP() const

Description

If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. getIRStackGuard must return nullptr if this returns true.

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:1624

virtual ~TargetLoweringBase()

Declared at: llvm/include/llvm/CodeGen/TargetLowering.h:231