class LSUnit

Declaration

class LSUnit : public LSUnitBase { /* full declaration omitted */ };

Description

Default Load/Store Unit (LS Unit) for simulated processors. Each load (or store) consumes one entry in the load (or store) queue. Rules are: 1) A younger load is allowed to pass an older load only if there are no stores nor barriers in between the two loads. 2) An younger store is not allowed to pass an older store. 3) A younger store is not allowed to pass an older load. 4) A younger load is allowed to pass an older store only if the load does not alias with the store. This class optimistically assumes that loads don't alias store operations. Under this assumption, younger loads are always allowed to pass older stores (this would only affects rule 4). Essentially, this class doesn't perform any sort alias analysis to identify aliasing loads and stores. To enforce aliasing between loads and stores, flag `AssumeNoAlias` must be set to `false` by the constructor of LSUnit. Note that this class doesn't know about the existence of different memory types for memory operations (example: write-through, write-combining, etc.). Derived classes are responsible for implementing that extra knowledge, and provide different sets of rules for loads and stores by overriding method `isReady()`. To emulate a write-combining memory type, rule 2. must be relaxed in a derived class to enable the reordering of non-aliasing store operations. No assumptions are made by this class on the size of the store buffer. This class doesn't know how to identify cases where store-to-load forwarding may occur. LSUnit doesn't attempt to predict whether a load or store hits or misses the L1 cache. To be more specific, LSUnit doesn't know anything about cache hierarchy and memory types. It only knows if an instruction "mayLoad" and/or "mayStore". For loads, the scheduling model provides an "optimistic" load-to-use latency (which usually matches the load-to-use latency for when there is a hit in the L1D). Derived classes may expand this knowledge. Class MCInstrDesc in LLVM doesn't know about serializing operations, nor memory-barrier like instructions. LSUnit conservatively assumes that an instruction which `mayLoad` and has `unmodeled side effects` behave like a "soft" load-barrier. That means, it serializes loads without forcing a flush of the load queue. Similarly, instructions that both `mayStore` and have `unmodeled side effects` are treated like store barriers. A full memory barrier is a 'mayLoad' and 'mayStore' instruction with unmodeled side effects. This is obviously inaccurate, but this is the best that we can do at the moment. Each load/store barrier consumes one entry in the load/store queue. A load/store barrier enforces ordering of loads/stores: - A younger load cannot pass a load barrier. - A younger store cannot pass a store barrier. A younger load has to wait for the memory load barrier to execute. A load/store barrier is "executed" when it becomes the oldest entry in the load/store queue(s). That also means, all the older loads/stores have already been executed.

Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:375

Inherits from: LSUnitBase

Method Overview

  • public LSUnit(const llvm::MCSchedModel & SM)
  • public LSUnit(const llvm::MCSchedModel & SM, unsigned int LQ, unsigned int SQ)
  • public LSUnit(const llvm::MCSchedModel & SM, unsigned int LQ, unsigned int SQ, bool AssumeNoAlias)
  • public unsigned int dispatch(const llvm::mca::InstRef & IR)
  • public llvm::mca::LSUnitBase::Status isAvailable(const llvm::mca::InstRef & IR) const
  • public void onInstructionExecuted(const llvm::mca::InstRef & IR)

Inherited from LSUnitBase:

Inherited from HardwareUnit:

    Methods

    LSUnit(const llvm::MCSchedModel& SM)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:419

    Parameters

    const llvm::MCSchedModel& SM

    LSUnit(const llvm::MCSchedModel& SM,
       unsigned int LQ,
       unsigned int SQ)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:421

    Parameters

    const llvm::MCSchedModel& SM
    unsigned int LQ
    unsigned int SQ

    LSUnit(const llvm::MCSchedModel& SM,
       unsigned int LQ,
       unsigned int SQ,
       bool AssumeNoAlias)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:423

    Parameters

    const llvm::MCSchedModel& SM
    unsigned int LQ
    unsigned int SQ
    bool AssumeNoAlias

    unsigned int dispatch(
    const llvm::mca::InstRef& IR)

    Description

    Allocates LS resources for instruction IR. This method assumes that a previous call to `isAvailable(IR)` succeeded returning LSU_AVAILABLE. Rules are: By default, rules are: 1. A store may not pass a previous store. 2. A load may not pass a previous store unless flag 'NoAlias' is set. 3. A load may pass a previous load. 4. A store may not pass a previous load (regardless of flag 'NoAlias'). 5. A load has to wait until an older load barrier is fully executed. 6. A store has to wait until an older store barrier is fully executed.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:444

    Parameters

    const llvm::mca::InstRef& IR

    llvm::mca::LSUnitBase::Status isAvailable(
    const llvm::mca::InstRef& IR) const

    Description

    Returns LSU_AVAILABLE if there are enough load/store queue entries to accomodate instruction IR.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:429

    Parameters

    const llvm::mca::InstRef& IR

    void onInstructionExecuted(
    const llvm::mca::InstRef& IR)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/LSUnit.h:446

    Parameters

    const llvm::mca::InstRef& IR