struct MCSchedModel

Declaration

struct MCSchedModel { /* full declaration omitted */ };

Description

Machine model for scheduling, bundling, and heuristics. The machine model directly provides basic information about the microarchitecture to the scheduler in the form of properties. It also optionally refers to scheduler resource tables and itinerary tables. Scheduler resource tables model the latency and cost for each instruction type. Itinerary tables are an independent mechanism that provides a detailed reservation table describing each cycle of instruction execution. Subtargets may define any or all of the above categories of data depending on the type of CPU and selected scheduler. The machine independent properties defined here are used by the scheduler as an abstract machine model. A real micro-architecture has a number of buffers, queues, and stages. Declaring that a given machine-independent abstract property corresponds to a specific physical property across all subtargets can't be done. Nonetheless, the abstract model is useful. Futhermore, subtargets typically extend this model with processor specific resources to model any hardware features that can be exploited by sceduling heuristics and aren't sufficiently represented in the abstract. The abstract pipeline is built around the notion of an "issue point". This is merely a reference point for counting machine cycles. The physical machine will have pipeline stages that delay execution. The scheduler does not model those delays because they are irrelevant as long as they are consistent. Inaccuracies arise when instructions have different execution delays relative to each other, in addition to their intrinsic latency. Those special cases can be handled by TableGen constructs such as, ReadAdvance, which reduces latency when reading data, and ResourceCycles, which consumes a processor resource when writing data for a number of abstract cycles. TODO: One tool currently missing is the ability to add a delay to ResourceCycles. That would be easy to add and would likely cover all cases currently handled by the legacy itinerary tables. A note on out-of-order execution and, more generally, instruction buffers. Part of the CPU pipeline is always in-order. The issue point, which is the point of reference for counting cycles, only makes sense as an in-order part of the pipeline. Other parts of the pipeline are sometimes falling behind and sometimes catching up. It's only interesting to model those other, decoupled parts of the pipeline if they may be predictably resource constrained in a way that the scheduler can exploit. The LLVM machine model distinguishes between in-order constraints and out-of-order constraints so that the target's scheduling strategy can apply appropriate heuristics. For a well-balanced CPU pipeline, out-of-order resources would not typically be treated as a hard scheduling constraint. For example, in the GenericScheduler, a delay caused by limited out-of-order resources is not directly reflected in the number of cycles that the scheduler sees between issuing an instruction and its dependent instructions. In other words, out-of-order resources don't directly increase the latency between pairs of instructions. However, they can still be used to detect potential bottlenecks across a sequence of instructions and bias the scheduling heuristics appropriately.

Declared at: llvm/include/llvm/MC/MCSchedule.h:244

Member Variables

public unsigned int IssueWidth
public unsigned int MicroOpBufferSize
public unsigned int LoopMicroOpBufferSize
public unsigned int LoadLatency
public unsigned int HighLatency
public unsigned int MispredictPenalty
public bool PostRAScheduler
public bool CompleteModel
public unsigned int ProcID
public const llvm::MCProcResourceDesc* ProcResourceTable
public const llvm::MCSchedClassDesc* SchedClassTable
public unsigned int NumProcResourceKinds
public unsigned int NumSchedClasses
public const llvm::InstrItinerary* InstrItineraries
public const llvm::MCExtraProcessorInfo* ExtraProcessorInfo
public static const unsigned int DefaultIssueWidth = 1
public static const unsigned int DefaultMicroOpBufferSize = 0
public static const unsigned int DefaultLoopMicroOpBufferSize = 0
public static const unsigned int DefaultLoadLatency = 4
public static const unsigned int DefaultHighLatency = 10
public static const unsigned int DefaultMispredictPenalty = 10
public static const llvm::MCSchedModel Default

Method Overview

Methods

static const llvm::MCSchedModel&
GetDefaultSchedModel()

Description

Returns the default initialized model.

Declared at: llvm/include/llvm/MC/MCSchedule.h:379

int computeInstrLatency(
    const llvm::MCSubtargetInfo& STI,
    const llvm::MCInstrInfo& MCII,
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCSchedule.h:358

Parameters

const llvm::MCSubtargetInfo& STI
const llvm::MCInstrInfo& MCII
const llvm::MCInst& Inst

int computeInstrLatency(
    const llvm::MCSubtargetInfo& STI,
    unsigned int SClass) const

Declared at: llvm/include/llvm/MC/MCSchedule.h:357

Parameters

const llvm::MCSubtargetInfo& STI
unsigned int SClass

static int computeInstrLatency(
    const llvm::MCSubtargetInfo& STI,
    const llvm::MCSchedClassDesc& SCDesc)

Description

Returns the latency value for the scheduling class.

Declared at: llvm/include/llvm/MC/MCSchedule.h:354

Parameters

const llvm::MCSubtargetInfo& STI
const llvm::MCSchedClassDesc& SCDesc

const llvm::MCExtraProcessorInfo&
getExtraProcessorInfo() const

Declared at: llvm/include/llvm/MC/MCSchedule.h:322

static unsigned int getForwardingDelayCycles(
    ArrayRef<llvm::MCReadAdvanceEntry> Entries,
    unsigned int WriteResourceIdx = 0)

Description

Returns the maximum forwarding delay for register reads dependent on writes of scheduling class WriteResourceIdx.

Declared at: llvm/include/llvm/MC/MCSchedule.h:375

Parameters

ArrayRef<llvm::MCReadAdvanceEntry> Entries
unsigned int WriteResourceIdx = 0

unsigned int getNumProcResourceKinds() const

Declared at: llvm/include/llvm/MC/MCSchedule.h:335

const llvm::MCProcResourceDesc* getProcResource(
    unsigned int ProcResourceIdx) const

Declared at: llvm/include/llvm/MC/MCSchedule.h:339

Parameters

unsigned int ProcResourceIdx

unsigned int getProcessorID() const

Declared at: llvm/include/llvm/MC/MCSchedule.h:317

static double getReciprocalThroughput(
    const llvm::MCSubtargetInfo& STI,
    const llvm::MCSchedClassDesc& SCDesc)

Declared at: llvm/include/llvm/MC/MCSchedule.h:363

Parameters

const llvm::MCSubtargetInfo& STI
const llvm::MCSchedClassDesc& SCDesc

static double getReciprocalThroughput(
    unsigned int SchedClass,
    const llvm::InstrItineraryData& IID)

Declared at: llvm/include/llvm/MC/MCSchedule.h:367

Parameters

unsigned int SchedClass
const llvm::InstrItineraryData& IID

double getReciprocalThroughput(
    const llvm::MCSubtargetInfo& STI,
    const llvm::MCInstrInfo& MCII,
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCSchedule.h:370

Parameters

const llvm::MCSubtargetInfo& STI
const llvm::MCInstrInfo& MCII
const llvm::MCInst& Inst

const llvm::MCSchedClassDesc* getSchedClassDesc(
    unsigned int SchedClassIdx) const

Declared at: llvm/include/llvm/MC/MCSchedule.h:346

Parameters

unsigned int SchedClassIdx

bool hasExtraProcessorInfo() const

Declared at: llvm/include/llvm/MC/MCSchedule.h:315

bool hasInstrSchedModel() const

Description

Does this machine model include instruction-level scheduling.

Declared at: llvm/include/llvm/MC/MCSchedule.h:320

bool isComplete() const

Description

Return true if this machine model data for all instructions with a scheduling class (itinerary class or SchedRW list).

Declared at: llvm/include/llvm/MC/MCSchedule.h:330

bool isOutOfOrder() const

Description

Return true if machine supports out of order execution.

Declared at: llvm/include/llvm/MC/MCSchedule.h:333