class Scheduler

Declaration

class Scheduler : public HardwareUnit { /* full declaration omitted */ };

Description

Class Scheduler is responsible for issuing instructions to pipeline resources. Internally, it delegates to a ResourceManager the management of processor resources. This class is also responsible for tracking the progress of instructions from the dispatch stage, until the write-back stage.

Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:70

Inherits from: HardwareUnit

Method Overview

  • public Scheduler(const llvm::MCSchedModel & Model, llvm::mca::LSUnitBase & Lsu, std::unique_ptr<SchedulerStrategy> SelectStrategy)
  • public Scheduler(std::unique_ptr<ResourceManager> RM, llvm::mca::LSUnitBase & Lsu, std::unique_ptr<SchedulerStrategy> SelectStrategy)
  • public Scheduler(const llvm::MCSchedModel & Model, llvm::mca::LSUnitBase & Lsu)
  • public void analyzeDataDependencies(SmallVectorImpl<llvm::mca::InstRef> & RegDeps, SmallVectorImpl<llvm::mca::InstRef> & MemDeps)
  • public uint64_t analyzeResourcePressure(SmallVectorImpl<llvm::mca::InstRef> & Insts)
  • public void cycleEvent(SmallVectorImpl<llvm::mca::ResourceRef> & Freed, SmallVectorImpl<llvm::mca::InstRef> & Executed, SmallVectorImpl<llvm::mca::InstRef> & Pending, SmallVectorImpl<llvm::mca::InstRef> & Ready)
  • public bool dispatch(llvm::mca::InstRef & IR)
  • public void dump() const
  • public unsigned int getResourceID(uint64_t Mask) const
  • public bool hadTokenStall() const
  • public llvm::mca::Scheduler::Status isAvailable(const llvm::mca::InstRef & IR)
  • public bool isReadySetEmpty() const
  • public bool isWaitSetEmpty() const
  • public void issueInstruction(llvm::mca::InstRef & IR, SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> & Used, SmallVectorImpl<llvm::mca::InstRef> & Pending, SmallVectorImpl<llvm::mca::InstRef> & Ready)
  • public bool mustIssueImmediately(const llvm::mca::InstRef & IR) const
  • public void sanityCheck(const llvm::mca::InstRef & IR) const
  • public llvm::mca::InstRef select()

Inherited from HardwareUnit:

    Methods

    Scheduler(const llvm::MCSchedModel& Model,
          llvm::mca::LSUnitBase& Lsu,
          std::unique_ptr<SchedulerStrategy>
              SelectStrategy)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:160

    Parameters

    const llvm::MCSchedModel& Model
    llvm::mca::LSUnitBase& Lsu
    std::unique_ptr<SchedulerStrategy> SelectStrategy

    Scheduler(std::unique_ptr<ResourceManager> RM,
          llvm::mca::LSUnitBase& Lsu,
          std::unique_ptr<SchedulerStrategy>
              SelectStrategy)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:165

    Parameters

    std::unique_ptr<ResourceManager> RM
    llvm::mca::LSUnitBase& Lsu
    std::unique_ptr<SchedulerStrategy> SelectStrategy

    Scheduler(const llvm::MCSchedModel& Model,
          llvm::mca::LSUnitBase& Lsu)

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:157

    Parameters

    const llvm::MCSchedModel& Model
    llvm::mca::LSUnitBase& Lsu

    void analyzeDataDependencies(
    SmallVectorImpl<llvm::mca::InstRef>& RegDeps,
    SmallVectorImpl<llvm::mca::InstRef>& MemDeps)

    Description

    This method is called by the ExecuteStage at the end of each cycle to identify bottlenecks caused by data dependencies. Vector RegDeps is populated by instructions that were not issued because of unsolved register dependencies. Vector MemDeps is populated by instructions that were not issued because of unsolved memory dependencies.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:251

    Parameters

    SmallVectorImpl<llvm::mca::InstRef>& RegDeps
    SmallVectorImpl<llvm::mca::InstRef>& MemDeps

    uint64_t analyzeResourcePressure(
    SmallVectorImpl<llvm::mca::InstRef>& Insts)

    Description

    Returns a mask of busy resources, and populates vector Insts with instructions that could not be issued to the underlying pipelines because not all pipeline resources were available.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:257

    Parameters

    SmallVectorImpl<llvm::mca::InstRef>& Insts

    void cycleEvent(
    SmallVectorImpl<llvm::mca::ResourceRef>&
        Freed,
    SmallVectorImpl<llvm::mca::InstRef>& Executed,
    SmallVectorImpl<llvm::mca::InstRef>& Pending,
    SmallVectorImpl<llvm::mca::InstRef>& Ready)

    Description

    This routine notifies the Scheduler that a new cycle just started. It notifies the underlying ResourceManager that a new cycle just started. Vector `Freed` is populated with resourceRef related to resources that have changed in state, and that are now available to new instructions. Instructions executed are added to vector Executed, while vector Ready is populated with instructions that have become ready in this new cycle. Vector Pending is popluated by instructions that have transitioned through the pending stat during this cycle. The Pending and Ready sets may not be disjoint. An instruction is allowed to transition from the WAIT state to the READY state (going through the PENDING state) within a single cycle. That means, instructions may appear in both the Pending and Ready set.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:225

    Parameters

    SmallVectorImpl<llvm::mca::ResourceRef>& Freed
    SmallVectorImpl<llvm::mca::InstRef>& Executed
    SmallVectorImpl<llvm::mca::InstRef>& Pending
    SmallVectorImpl<llvm::mca::InstRef>& Ready

    bool dispatch(llvm::mca::InstRef& IR)

    Description

    Reserves buffer and LSUnit queue resources that are necessary to issue this instruction. Returns true if instruction IR is ready to be issued to the underlying pipelines. Note that this operation cannot fail; it assumes that a previous call to method `isAvailable(IR)` returned `SC_AVAILABLE`. If IR is a memory operation, then the Scheduler queries the LS unit to obtain a LS token. An LS token is used internally to track memory dependencies.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:198

    Parameters

    llvm::mca::InstRef& IR

    void dump() const

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:265

    unsigned int getResourceID(uint64_t Mask) const

    Description

    Convert a resource mask into a valid llvm processor resource identifier. Only the most significant bit of the Mask is used by this method to identify the processor resource.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:234

    Parameters

    uint64_t Mask

    bool hadTokenStall() const

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:261

    llvm::mca::Scheduler::Status isAvailable(
    const llvm::mca::InstRef& IR)

    Description

    Check if the instruction in 'IR' can be dispatched during this cycle. Return SC_AVAILABLE if both scheduler and LS resources are available. This method is also responsible for setting field HadTokenStall if IR cannot be dispatched to the Scheduler due to unavailable resources.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:186

    Parameters

    const llvm::mca::InstRef& IR

    bool isReadySetEmpty() const

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:243

    bool isWaitSetEmpty() const

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:244

    void issueInstruction(
    llvm::mca::InstRef& IR,
    SmallVectorImpl<
        std::pair<ResourceRef, ResourceCycles>>&
        Used,
    SmallVectorImpl<llvm::mca::InstRef>& Pending,
    SmallVectorImpl<llvm::mca::InstRef>& Ready)

    Description

    Issue an instruction and populates a vector of used pipeline resources, and a vector of instructions that transitioned to the ready state as a result of this event.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:203

    Parameters

    llvm::mca::InstRef& IR
    SmallVectorImpl< std::pair<ResourceRef, ResourceCycles>>& Used
    SmallVectorImpl<llvm::mca::InstRef>& Pending
    SmallVectorImpl<llvm::mca::InstRef>& Ready

    bool mustIssueImmediately(
    const llvm::mca::InstRef& IR) const

    Description

    Returns true if IR has to be issued immediately, or if IR is a zero latency instruction.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:211

    Parameters

    const llvm::mca::InstRef& IR

    void sanityCheck(
    const llvm::mca::InstRef& IR) const

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:269

    Parameters

    const llvm::mca::InstRef& IR

    llvm::mca::InstRef select()

    Description

    Select the next instruction to issue from the ReadySet. Returns an invalid instruction reference if there are no ready instructions, or if processor resources are not available.

    Declared at: llvm/include/llvm/MCA/HardwareUnits/Scheduler.h:241