ΒΆllvm::ScheduleDAGSDNodes*
createHybridListDAGScheduler(
llvm::SelectionDAGISel* IS,
CodeGenOpt::Level)
llvm::ScheduleDAGSDNodes*
createHybridListDAGScheduler(
llvm::SelectionDAGISel* IS,
CodeGenOpt::Level)Description
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that make use of latency information to avoid stalls for long latency instructions in low register pressure mode. In high register pressure mode it schedules to reduce register pressure.
Declared at: llvm/include/llvm/CodeGen/SchedulerRegistry.h:75
Parameters
- llvm::SelectionDAGISel* IS
- CodeGenOpt::Level