class ScheduleDAGSDNodes

Declaration

class ScheduleDAGSDNodes : public ScheduleDAG { /* full declaration omitted */ };

Description

ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs. Edges between SUnits are initially based on edges in the SelectionDAG, and additional edges can be added by the schedulers as heuristics. SDNodes such as Constants, Registers, and a few others that are not interesting to schedulers are not allocated SUnits. SDNodes with MVT::Glue operands are grouped along with the flagged nodes into a single SUnit so that they are scheduled together. SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output edges. Physical register dependence information is not carried in the DAG and must be handled explicitly by schedulers.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:46

Inherits from: ScheduleDAG

Member Variables

public llvm::MachineBasicBlock* BB
public llvm::SelectionDAG* DAG
public const llvm::InstrItineraryData* InstrItins
public std::vector<SUnit*> Sequence
The schedule. Null SUnit*'s represent noop instructions.

Inherited from ScheduleDAG:

public TM
public TII
public TRI
public MF
public MRI
public SUnits
public EntrySU
public ExitSU
public StressSched

Method Overview

Inherited from ScheduleDAG:

Methods

void BuildSchedGraph(llvm::AAResults* AA)

Description

BuildSchedGraph - Build the SUnit graph from the selection dag that we are input. This SUnit graph is similar to the SelectionDAG, but excludes nodes that aren't interesting to scheduling, and represents flagged together nodes with a single SUnit.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:97

Parameters

llvm::AAResults* AA

llvm::SUnit* Clone(llvm::SUnit* Old)

Description

Clone - Creates a clone of the specified SUnit. It does not copy the predecessors / successors info nor the temporary scheduling states.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:91

Parameters

llvm::SUnit* Old

virtual llvm::MachineBasicBlock* EmitSchedule(
    MachineBasicBlock::iterator& InsertPos)

Description

EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Sequence.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:123

Parameters

MachineBasicBlock::iterator& InsertPos

void InitNumRegDefsLeft(llvm::SUnit* SU)

Description

InitNumRegDefsLeft - Determine the # of regs defined by this node.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:101

Parameters

llvm::SUnit* SU

void Run(llvm::SelectionDAG* dag,
         llvm::MachineBasicBlock* bb)

Description

Run - perform scheduling.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:61

Parameters

llvm::SelectionDAG* dag
llvm::MachineBasicBlock* bb

virtual void Schedule()

Description

Schedule - Order nodes according to selected style, filling in the Sequence member.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:113

ScheduleDAGSDNodes(llvm::MachineFunction& mf)

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:55

Parameters

llvm::MachineFunction& mf

void VerifyScheduledSequence(bool isBottomUp)

Description

VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of scheduled instructions.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:117

Parameters

bool isBottomUp

virtual void computeLatency(llvm::SUnit* SU)

Description

computeLatency - Compute node latency.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:105

Parameters

llvm::SUnit* SU

virtual void computeOperandLatency(
    llvm::SDNode* Def,
    llvm::SDNode* Use,
    unsigned int OpIdx,
    llvm::SDep& dep) const

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:107

Parameters

llvm::SDNode* Def
llvm::SDNode* Use
unsigned int OpIdx
llvm::SDep& dep

void dump() const

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:126

void dumpNode(const llvm::SUnit& SU) const

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:125

Parameters

const llvm::SUnit& SU

void dumpSchedule() const

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:127

virtual bool forceUnitLatencies() const

Description

ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one. The default is to return false; schedulers may override this as needed.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:173

virtual void getCustomGraphFeatures(
    GraphWriter<llvm::ScheduleDAG*>& GW) const

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:133

Parameters

GraphWriter<llvm::ScheduleDAG*>& GW

std::string getDAGName() const

Description

Return the basic block label.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:131

std::string getGraphNodeLabel(
    const llvm::SUnit* SU) const

Description

Returns a label for an SUnit node in a visualization of the ScheduleDAG.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:129

Parameters

const llvm::SUnit* SU

static bool isPassiveNode(llvm::SDNode* Node)

Description

isPassiveNode - Return true if the node is a non-scheduled leaf.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:65

Parameters

llvm::SDNode* Node

llvm::SUnit* newSUnit(llvm::SDNode* N)

Description

NewSUnit - Creates a new SUnit and return a ptr to it.

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:86

Parameters

llvm::SDNode* N

~ScheduleDAGSDNodes()

Declared at: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h:57