class MachineIRBuilder

Declaration

class MachineIRBuilder { /* full declaration omitted */ };

Description

Helper class to build MachineInstr. It keeps internally the insertion point and debug location for all the new instructions we want to create. This information can be modify via the related setters.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:221

Method Overview

public MachineIRBuilder()
public MachineIRBuilder(llvm::MachineFunction & MF)
public MachineIRBuilder(llvm::MachineInstr & MI)
public MachineIRBuilder(const llvm::MachineIRBuilderState & BState)
public llvm::MachineInstrBuilder buildAShr(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildAdd(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildAddrSpaceCast(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildAnd(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildAnyExt(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildAnyExtOrTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildAtomicCmpXchg(llvm::Register OldValRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicCmpXchgWithSuccess(llvm::Register OldValRes, llvm::Register SuccessRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMW(unsigned int Opcode, const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWAdd(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWAnd(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWFAdd(const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWFSub(const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWMax(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWMin(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWNand(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWOr(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWSub(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWUmax(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWUmin(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWXchg(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWXor(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildBitcast(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildBlockAddress(llvm::Register Res, const llvm::BlockAddress * BA)
public llvm::MachineInstrBuilder buildBoolExt(const llvm::DstOp & Res, const llvm::SrcOp & Op, bool IsFP)
public llvm::MachineInstrBuilder buildBr(llvm::MachineBasicBlock & Dest)
public llvm::MachineInstrBuilder buildBrCond(llvm::Register Tst, llvm::MachineBasicBlock & Dest)
public llvm::MachineInstrBuilder buildBrIndirect(llvm::Register Tgt)
public llvm::MachineInstrBuilder buildBrJT(llvm::Register TablePtr, unsigned int JTI, llvm::Register IndexReg)
public llvm::MachineInstrBuilder buildBuildVector(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildBuildVectorTrunc(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildCTLZ(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTPOP(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTTZ(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCast(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildConcatVectors(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildConstDbgValue(const llvm::Constant & C, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildConstant(const llvm::DstOp & Res, int64_t Val)
public llvm::MachineInstrBuilder buildConstant(const llvm::DstOp & Res, const llvm::APInt & Val)
public virtual llvm::MachineInstrBuilder buildConstant(const llvm::DstOp & Res, const llvm::ConstantInt & Val)
public llvm::MachineInstrBuilder buildCopy(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildDbgLabel(const llvm::MDNode * Label)
public llvm::MachineInstrBuilder buildDirectDbgValue(llvm::Register Reg, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildDynStackAlloc(const llvm::DstOp & Res, const llvm::SrcOp & Size, unsigned int Align)
public llvm::MachineInstrBuilder buildExtOrTrunc(unsigned int ExtOpc, const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildExtract(const llvm::DstOp & Res, const llvm::SrcOp & Src, uint64_t Index)
public llvm::MachineInstrBuilder buildExtractVectorElement(const llvm::DstOp & Res, const llvm::SrcOp & Val, const llvm::SrcOp & Idx)
public llvm::MachineInstrBuilder buildFAbs(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFAdd(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFCanonicalize(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, Optional<unsigned int> Flags = None)
public virtual llvm::MachineInstrBuilder buildFConstant(const llvm::DstOp & Res, const llvm::ConstantFP & Val)
public llvm::MachineInstrBuilder buildFConstant(const llvm::DstOp & Res, double Val)
public llvm::MachineInstrBuilder buildFConstant(const llvm::DstOp & Res, const llvm::APFloat & Val)
public llvm::MachineInstrBuilder buildFCopysign(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildFIDbgValue(int FI, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildFMA(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, const llvm::SrcOp & Src2, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMAD(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, const llvm::SrcOp & Src2, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMul(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFNeg(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFPExt(const llvm::DstOp & Res, const llvm::SrcOp & Op, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFPTOSI(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildFPTOUI(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildFPTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op, Optional<unsigned int> FLags = None)
public llvm::MachineInstrBuilder buildFSub(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildFence(unsigned int Ordering, unsigned int Scope)
public llvm::MachineInstrBuilder buildFrameIndex(const llvm::DstOp & Res, int Idx)
public llvm::MachineInstrBuilder buildGlobalValue(const llvm::DstOp & Res, const llvm::GlobalValue * GV)
public llvm::MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildIndirectDbgValue(llvm::Register Reg, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildInsert(llvm::Register Res, llvm::Register Src, llvm::Register Op, unsigned int Index)
public llvm::MachineInstrBuilder buildInsertVectorElement(const llvm::DstOp & Res, const llvm::SrcOp & Val, const llvm::SrcOp & Elt, const llvm::SrcOp & Idx)
public virtual llvm::MachineInstrBuilder buildInstr(unsigned int Opc, ArrayRef<llvm::DstOp> DstOps, ArrayRef<llvm::SrcOp> SrcOps, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildInstr(unsigned int Opcode)
public llvm::MachineInstrBuilder buildInstrNoInsert(unsigned int Opcode)
public llvm::MachineInstrBuilder buildIntToPtr(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<llvm::Register> Res, bool HasSideEffects)
public llvm::MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<llvm::DstOp> Res, bool HasSideEffects)
public llvm::MachineInstrBuilder buildIntrinsicTrunc(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildJumpTable(const llvm::LLT PtrTy, unsigned int JTI)
public llvm::MachineInstrBuilder buildLShr(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildLoad(const llvm::DstOp & Res, const llvm::SrcOp & Addr, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildLoadInstr(unsigned int Opcode, const llvm::DstOp & Res, const llvm::SrcOp & Addr, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildMerge(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildMul(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildNot(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildOr(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildPtrAdd(const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildPtrMask(const llvm::DstOp & Res, const llvm::SrcOp & Op0, uint32_t NumBits)
public llvm::MachineInstrBuilder buildPtrToInt(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildSExt(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildSExtOrTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildSITOFP(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildSMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildSMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildSMulH(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildSelect(const llvm::DstOp & Res, const llvm::SrcOp & Tst, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, Optional<unsigned int> Flags = None)
public void buildSequence(llvm::Register Res, ArrayRef<llvm::Register> Ops, ArrayRef<uint64_t> Indices)
public llvm::MachineInstrBuilder buildShl(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildSplatVector(const llvm::DstOp & Res, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildStore(const llvm::SrcOp & Val, const llvm::SrcOp & Addr, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildSub(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildUAdde(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, const llvm::SrcOp & CarryIn)
public llvm::MachineInstrBuilder buildUAddo(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildUITOFP(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildUMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildUMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildUMulH(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildUndef(const llvm::DstOp & Res)
public llvm::MachineInstrBuilder buildUnmerge(llvm::LLT Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildUnmerge(ArrayRef<llvm::LLT> Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildUnmerge(ArrayRef<llvm::Register> Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildXor(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildZExt(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildZExtOrTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public unsigned int getBoolExtOp(bool IsVec, bool IsFP) const
public llvm::GISelCSEInfo * getCSEInfo()
public const llvm::GISelCSEInfo * getCSEInfo() const
public const llvm::DebugLoc & getDL()
public const llvm::DataLayout & getDataLayout() const
public llvm::DebugLoc getDebugLoc()
public MachineBasicBlock::iterator getInsertPt()
public llvm::MachineBasicBlock & getMBB()
public const llvm::MachineBasicBlock & getMBB() const
public llvm::MachineFunction & getMF()
public const llvm::MachineFunction & getMF() const
public const llvm::MachineRegisterInfo * getMRI() const
public llvm::MachineRegisterInfo * getMRI()
public llvm::MachineIRBuilderState & getState()
public const llvm::TargetInstrInfo & getTII()
public llvm::MachineInstrBuilder insertInstr(llvm::MachineInstrBuilder MIB)
public Optional<llvm::MachineInstrBuilder> materializePtrAdd(llvm::Register & Res, llvm::Register Op0, const llvm::LLT & ValueTy, uint64_t Value)
protected void recordInsertion(llvm::MachineInstr * MI) const
public void setCSEInfo(llvm::GISelCSEInfo * Info)
public void setChangeObserver(llvm::GISelChangeObserver & Observer)
public void setDebugLoc(const llvm::DebugLoc & DL)
public void setInsertPt(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator II)
public void setInstr(llvm::MachineInstr & MI)
public void setMBB(llvm::MachineBasicBlock & MBB)
public void setMF(llvm::MachineFunction & MF)
public void stopObservingChanges()
protected void validateBinaryOp(const llvm::LLT & Res, const llvm::LLT & Op0, const llvm::LLT & Op1)
protected void validateSelectOp(const llvm::LLT & ResTy, const llvm::LLT & TstTy, const llvm::LLT & Op0Ty, const llvm::LLT & Op1Ty)
protected void validateShiftOp(const llvm::LLT & Res, const llvm::LLT & Op0, const llvm::LLT & Op1)
protected void validateTruncExt(const llvm::LLT & Dst, const llvm::LLT & Src, bool IsExtend)
public virtual ~MachineIRBuilder()

Methods

¶MachineIRBuilder()

Description

Some constructors for easy use.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:237

¶MachineIRBuilder(llvm::MachineFunction& MF)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:238

Parameters

llvm::MachineFunction& MF

¶MachineIRBuilder(llvm::MachineInstr& MI)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:239

Parameters

llvm::MachineInstr& MI

¶MachineIRBuilder(
    const llvm::MachineIRBuilderState& BState)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:245

Parameters

const llvm::MachineIRBuilderState& BState

¶llvm::MachineInstrBuilder buildAShr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1295

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_ADD \p Op0, \p Op1 G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1, truncated to their width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1226

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAddrSpaceCast(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_ADDRSPACE_CAST \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:544

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildAnd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_AND \p Op0, \p Op1 G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p Op1.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1312

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAnyExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_ANYEXT \p Op0 G_ANYEXT produces a register of the specified width, with bits 0 to sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified (i.e. this is neither zero nor sign-extension). For a vector register, each element is extended individually.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:505

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildAnyExtOrTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

\p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:599

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicCmpXchg(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register CmpVal,
    llvm::Register NewVal,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO`. Atomically replace the value at \p Addr with \p NewVal if it is currently\p CmpVal otherwise leaves it unchanged. Puts the original value from \p Addr in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1001

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register CmpVal
llvm::Register NewVal
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder
buildAtomicCmpXchgWithSuccess(
    llvm::Register OldValRes,
    llvm::Register SuccessRes,
    llvm::Register Addr,
    llvm::Register CmpVal,
    llvm::Register NewVal,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def >, SuccessRes <def > = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. Atomically replace the value at \p Addr with \p NewVal if it is currently\p CmpVal otherwise leaves it unchanged. Puts the original value from \p Addr in \p Res, along with an s1 indicating whether it was replaced.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:983

Parameters

llvm::Register OldValRes
llvm::Register SuccessRes
llvm::Register Addr
llvm::Register CmpVal
llvm::Register NewVal
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMW(
    unsigned int Opcode,
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_ <Opcode > Addr, Val, MMO`. Atomically read-modify-update the value at \p Addr with \p Val. Puts the original value from \p Addr in \p OldValRes. The modification is determined by the opcode.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1018

Parameters

unsigned int Opcode
const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWAdd(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_ADD Addr, Val, MMO`. Atomically replace the value at \p Addr with the addition of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1049

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWAnd(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_AND Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise and of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1079

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWFAdd(
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_FADD Addr, Val, MMO`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1193

Parameters

const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

¶llvm::MachineInstrBuilder buildAtomicRMWFSub(
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_FSUB Addr, Val, MMO`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1198

Parameters

const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

¶llvm::MachineInstrBuilder buildAtomicRMWMax(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_MAX Addr, Val, MMO`. Atomically replace the value at \p Addr with the signed maximum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1141

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWMin(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_MIN Addr, Val, MMO`. Atomically replace the value at \p Addr with the signed minimum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1157

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWNand(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_NAND Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise nand of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1095

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWOr(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_OR Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise or of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1110

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWSub(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_SUB Addr, Val, MMO`. Atomically replace the value at \p Addr with the subtraction of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1064

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWUmax(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_UMAX Addr, Val, MMO`. Atomically replace the value at \p Addr with the unsigned maximum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1173

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWUmin(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_UMIN Addr, Val, MMO`. Atomically replace the value at \p Addr with the unsigned minimum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1189

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWXchg(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_XCHG Addr, Val, MMO`. Atomically replace the value at \p Addr with \p Val. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1034

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWXor(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_XOR Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise xor of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1125

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBitcast(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_BITCAST \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:539

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildBlockAddress(
    llvm::Register Res,
    const llvm::BlockAddress* BA)

Description

Build and insert \p Res = G_BLOCK_ADDR \p BA G_BLOCK_ADDR computes the address of a basic block.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1213

Parameters

llvm::Register Res
const llvm::BlockAddress* BA

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildBoolExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    bool IsFP)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:554

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
bool IsFP

¶llvm::MachineInstrBuilder buildBr(
    llvm::MachineBasicBlock& Dest)

Description

Build and insert G_BR \p Dest G_BR is an unconditional branch to \p Dest.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:623

Parameters

llvm::MachineBasicBlock& Dest

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBrCond(
    llvm::Register Tst,
    llvm::MachineBasicBlock& Dest)

Description

Build and insert G_BRCOND \p Tst, \p Dest G_BRCOND is a conditional branch to \p Dest.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:637

Parameters

llvm::Register Tst
llvm::MachineBasicBlock& Dest

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildBrIndirect(
    llvm::Register Tgt)

Description

Build and insert G_BRINDIRECT \p Tgt G_BRINDIRECT is an indirect branch to \p Tgt.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:647

Parameters

llvm::Register Tgt

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBrJT(
    llvm::Register TablePtr,
    unsigned int JTI,
    llvm::Register IndexReg)

Description

Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg G_BRJT is a jump table branch using a table base pointer \p TablePtr, jump table index \p JTI and index \p IndexReg

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:660

Parameters

llvm::Register TablePtr
unsigned int JTI
llvm::Register IndexReg

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBuildVector(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... G_BUILD_VECTOR creates a vector value from multiple scalar registers.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:812

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBuildVectorTrunc(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ... G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers which have types larger than the destination vector element type, and truncates the values to fit. If the operands given are already the same size as the vector elt type, then this method will instead create a G_BUILD_VECTOR instruction.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:833

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildCTLZ(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTLZ \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1352

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTLZ_ZERO_UNDEF(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1357

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTPOP(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTPOP \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1347

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTTZ(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTTZ \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1362

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTTZ_ZERO_UNDEF(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1367

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCast(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert an appropriate cast between two registers of equal size.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:614

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildConcatVectors(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ... G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more vectors.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:847

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildConstDbgValue(
    const llvm::Constant& C,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instructions specifying that \p Variable is given by \p C (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:365

Parameters

const llvm::Constant& C
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildConstant(
    const llvm::DstOp& Res,
    int64_t Val)

Description

Build and insert \p Res = G_CONSTANT \p Val G_CONSTANT is an integer constant with the specified size and value.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:684

Parameters

const llvm::DstOp& Res
int64_t Val

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildConstant(
    const llvm::DstOp& Res,
    const llvm::APInt& Val)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:685

Parameters

const llvm::DstOp& Res
const llvm::APInt& Val

¶virtual llvm::MachineInstrBuilder buildConstant(
    const llvm::DstOp& Res,
    const llvm::ConstantInt& Val)

Description

Build and insert \p Res = G_CONSTANT \p Val G_CONSTANT is an integer constant with the specified size and value. \p Val will be extended or truncated to the size of \p Reg.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:673

Parameters

const llvm::DstOp& Res
const llvm::ConstantInt& Val

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildCopy(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = COPY Op Register-to-register COPY sets \p Res to \p Op.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:709

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildDbgLabel(
    const llvm::MDNode* Label)

Description

Build and insert a DBG_LABEL instructions specifying that \p Label is given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:371

Parameters

const llvm::MDNode* Label

¶llvm::MachineInstrBuilder buildDirectDbgValue(
    llvm::Register Reg,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instruction expressing the fact that the associated \p Variable lives in \p Reg (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:347

Parameters

llvm::Register Reg
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildDynStackAlloc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Size,
    unsigned int Align)

Description

Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of the allocated memory into \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:381

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Size
unsigned int Align

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildExtOrTrunc(
    unsigned int ExtOpc,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and\p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:610

Parameters

unsigned int ExtOpc
const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildExtract(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src,
    uint64_t Index)

Description

Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:753

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src
uint64_t Index

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder
buildExtractVectorElement(const llvm::DstOp& Res,
                          const llvm::SrcOp& Val,
                          const llvm::SrcOp& Idx)

Description

Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:962

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Val
const llvm::SrcOp& Idx

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildFAbs(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FABS \p Op0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1405

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FADD \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1372

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFCanonicalize(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_FCANONICALIZE \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1411

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFCmp(
    CmpInst::Predicate Pred,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:921

Parameters

CmpInst::Predicate Pred
const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶virtual llvm::MachineInstrBuilder buildFConstant(
    const llvm::DstOp& Res,
    const llvm::ConstantFP& Val)

Description

Build and insert \p Res = G_FCONSTANT \p Val G_FCONSTANT is a floating-point constant with the specified size and value.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:696

Parameters

const llvm::DstOp& Res
const llvm::ConstantFP& Val

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildFConstant(
    const llvm::DstOp& Res,
    double Val)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:699

Parameters

const llvm::DstOp& Res
double Val

¶llvm::MachineInstrBuilder buildFConstant(
    const llvm::DstOp& Res,
    const llvm::APFloat& Val)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:700

Parameters

const llvm::DstOp& Res
const llvm::APFloat& Val

¶llvm::MachineInstrBuilder buildFCopysign(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1423

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildFIDbgValue(
    int FI,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instruction expressing the fact that the associated \p Variable lives in the stack slot specified by \p FI (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:360

Parameters

int FI
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildFMA(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    const llvm::SrcOp& Src2,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1385

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
const llvm::SrcOp& Src2
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMAD(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    const llvm::SrcOp& Src2,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1392

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
const llvm::SrcOp& Src2
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1277

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFNeg(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FNEG \p Op0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1399

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFPExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FPEXT \p Op

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:522

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFPTOSI(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_FPTOSI \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1444

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildFPTOUI(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_FPTOUI \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1439

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildFPTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    Optional<unsigned int> FLags = None)

Description

Build and insert \p Res = G_FPTRUNC \p Op G_FPTRUNC converts a floating-point value into one with a smaller type.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:878

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
Optional<unsigned int> FLags = None

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildFSub(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_FSUB \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1379

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildFence(
    unsigned int Ordering,
    unsigned int Scope)

Description

Build and insert `G_FENCE Ordering, Scope`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1203

Parameters

unsigned int Ordering
unsigned int Scope

¶llvm::MachineInstrBuilder buildFrameIndex(
    const llvm::DstOp& Res,
    int Idx)

Description

Build and insert \p Res = G_FRAME_INDEX \p Idx G_FRAME_INDEX materializes the address of an alloca value or other stack-based object.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:393

Parameters

const llvm::DstOp& Res
int Idx

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildGlobalValue(
    const llvm::DstOp& Res,
    const llvm::GlobalValue* GV)

Description

Build and insert \p Res = G_GLOBAL_VALUE \p GV G_GLOBAL_VALUE materializes the address of the specified global into \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:405

Parameters

const llvm::DstOp& Res
const llvm::GlobalValue* GV

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildICmp(
    CmpInst::Predicate Pred,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:906

Parameters

CmpInst::Predicate Pred
const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildIndirectDbgValue(
    llvm::Register Reg,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instruction expressing the fact that the associated \p Variable lives in memory at \p Reg (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:353

Parameters

llvm::Register Reg
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildInsert(
    llvm::Register Res,
    llvm::Register Src,
    llvm::Register Op,
    unsigned int Index)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:850

Parameters

llvm::Register Res
llvm::Register Src
llvm::Register Op
unsigned int Index

¶llvm::MachineInstrBuilder
buildInsertVectorElement(const llvm::DstOp& Res,
                         const llvm::SrcOp& Val,
                         const llvm::SrcOp& Elt,
                         const llvm::SrcOp& Idx)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:949

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Val
const llvm::SrcOp& Elt
const llvm::SrcOp& Idx

Returns

The newly created instruction.

¶virtual llvm::MachineInstrBuilder buildInstr(
    unsigned int Opc,
    ArrayRef<llvm::DstOp> DstOps,
    ArrayRef<llvm::SrcOp> SrcOps,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1480

Parameters

unsigned int Opc
ArrayRef<llvm::DstOp> DstOps
ArrayRef<llvm::SrcOp> SrcOps
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildInstr(
    unsigned int Opcode)

Description

Build and insert <empty > = \p Opcode <empty >. The insertion point is the one set by the last call of either setBasicBlock or setMI.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:333

Parameters

unsigned int Opcode

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildInstrNoInsert(
    unsigned int Opcode)

Description

Build but don't insert <empty > = \p Opcode <empty >.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:340

Parameters

unsigned int Opcode

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildIntToPtr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert a G_INTTOPTR instruction.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:534

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildIntrinsic(
    Intrinsic::ID ID,
    ArrayRef<llvm::Register> Res,
    bool HasSideEffects)

Description

Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the result register definition unless \p Reg is NoReg (== 0). The second operand will be the intrinsic's ID. Callers are expected to add the required definitions and uses afterwards.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:863

Parameters

Intrinsic::ID ID
ArrayRef<llvm::Register> Res
bool HasSideEffects

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildIntrinsic(
    Intrinsic::ID ID,
    ArrayRef<llvm::DstOp> Res,
    bool HasSideEffects)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:865

Parameters

Intrinsic::ID ID
ArrayRef<llvm::DstOp> Res
bool HasSideEffects

¶llvm::MachineInstrBuilder buildIntrinsicTrunc(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1417

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildJumpTable(
    const llvm::LLT PtrTy,
    unsigned int JTI)

Description

Build and insert \p Res = G_JUMP_TABLE \p JTI G_JUMP_TABLE sets \p Res to the address of the jump table specified by the jump table index \p JTI.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1478

Parameters

const llvm::LLT PtrTy
unsigned int JTI

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildLShr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1289

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildLoad(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Addr,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `Res = G_LOAD Addr, MMO`. Loads the value stored at \p Addr. Puts the result in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:720

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Addr
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildLoadInstr(
    unsigned int Opcode,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Addr,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `Res = <opcode > Addr, MMO`. Loads the value stored at \p Addr. Puts the result in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:732

Parameters

unsigned int Opcode
const llvm::DstOp& Res
const llvm::SrcOp& Addr
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildMerge(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_MERGE_VALUES \p Op0, ... G_MERGE_VALUES combines the input elements contiguously into a larger register.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:785

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_MUL \p Op0, \p Op1 G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1, truncated to their width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1259

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildNot(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert a bitwise not,\p NegOne = G_CONSTANT -1\p Res = G_OR \p Op0, NegOne

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1341

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildOr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_OR \p Op0, \p Op1 G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p Op1.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1327

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildPtrAdd(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1 G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0, storing the resulting pointer in \p Res. Addressible units are typically bytes but this can vary between targets.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:419

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildPtrMask(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    uint32_t NumBits)

Description

Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits G_PTR_MASK clears the low bits of a pointer operand without destroying its pointer properties. This has the effect of rounding the address *down* to a specified alignment in bits.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:455

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0
uint32_t NumBits

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildPtrToInt(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert a G_PTRTOINT instruction.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:529

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildSExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_SEXT \p Op G_SEXT produces a register of the specified width, with bits 0 to sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the high bit of \p Op (i.e. 2s-complement sign extended).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:519

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildSExtOrTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or\p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:579

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildSITOFP(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_SITOFP \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1434

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildSMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_SMAX \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1455

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildSMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_SMIN \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1449

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildSMulH(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1271

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildSelect(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Tst,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    Optional<unsigned int> Flags = None)

Description

Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:935

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Tst
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶void buildSequence(llvm::Register Res,
                   ArrayRef<llvm::Register> Ops,
                   ArrayRef<uint64_t> Indices)

Description

Build and insert instructions to put \p Ops together at the specified p Indices to form a larger register. If the types of the input registers are uniform and cover the entirity of\p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF followed by a sequence of G_INSERT instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:771

Parameters

llvm::Register Res
ArrayRef<llvm::Register> Ops
ArrayRef<uint64_t> Indices

¶llvm::MachineInstrBuilder buildShl(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1283

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildSplatVector(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill the number of elements

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:817

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildStore(
    const llvm::SrcOp& Val,
    const llvm::SrcOp& Addr,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `G_STORE Val, Addr, MMO`. Stores the value \p Val to \p Addr.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:744

Parameters

const llvm::SrcOp& Val
const llvm::SrcOp& Addr
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildSub(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_SUB \p Op0, \p Op1 G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1, truncated to their width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1243

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_TRUNC \p Op G_TRUNC extracts the low bits of a type. For a vector type each element is truncated independently before being packed into the destination.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:892

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildUAdde(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    const llvm::SrcOp& CarryIn)

Description

Build and insert \p Res, \p CarryOut = G_UADDE \p Op0, \p Op1, \p CarryIn G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit width) and sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:487

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
const llvm::SrcOp& CarryIn

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildUAddo(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1 G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:470

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildUITOFP(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_UITOFP \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1429

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildUMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_UMAX \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1467

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildUMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_UMIN \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1461

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildUMulH(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1265

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildUndef(
    const llvm::DstOp& Res)

Description

Build and insert \p Res = IMPLICIT_DEF.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:756

Parameters

const llvm::DstOp& Res

¶llvm::MachineInstrBuilder buildUnmerge(
    llvm::LLT Res,
    const llvm::SrcOp& Op)

Description

Build and insert an unmerge of \p Res sized pieces to cover \p Op

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:801

Parameters

llvm::LLT Res
const llvm::SrcOp& Op

¶llvm::MachineInstrBuilder buildUnmerge(
    ArrayRef<llvm::LLT> Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op G_UNMERGE_VALUES splits contiguous bits of the input into multiple

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:797

Parameters

ArrayRef<llvm::LLT> Res
const llvm::SrcOp& Op

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildUnmerge(
    ArrayRef<llvm::Register> Res,
    const llvm::SrcOp& Op)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:798

Parameters

ArrayRef<llvm::Register> Res
const llvm::SrcOp& Op

¶llvm::MachineInstrBuilder buildXor(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_XOR \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1333

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildZExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_ZEXT \p Op G_ZEXT produces a register of the specified width, with bits 0 to sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector register, each element is extended individually.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:569

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildZExtOrTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or\p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:589

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶unsigned int getBoolExtOp(bool IsVec,
                          bool IsFP) const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:550

Parameters

bool IsVec
bool IsFP

Returns

The opcode of the extension the target wants to use for boolean values.

¶llvm::GISelCSEInfo* getCSEInfo()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:288

¶const llvm::GISelCSEInfo* getCSEInfo() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:289

¶const llvm::DebugLoc& getDL()

Description

Getter for DebugLoc

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:268

¶const llvm::DataLayout& getDataLayout() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:263

¶llvm::DebugLoc getDebugLoc()

Description

Get the current instruction's debug location.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:324

¶MachineBasicBlock::iterator getInsertPt()

Description

Current insertion point for new instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:292

¶llvm::MachineBasicBlock& getMBB()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:283

¶const llvm::MachineBasicBlock& getMBB() const

Description

Getter for the basic block we currently build.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:278

¶llvm::MachineFunction& getMF()

Description

Getter for the function we currently build.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:253

¶const llvm::MachineFunction& getMF() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:258

¶const llvm::MachineRegisterInfo* getMRI() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:272

¶llvm::MachineRegisterInfo* getMRI()

Description

Getter for MRI

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:271

¶llvm::MachineIRBuilderState& getState()

Description

Getter for the State

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:275

¶const llvm::TargetInstrInfo& getTII()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:247

¶llvm::MachineInstrBuilder insertInstr(
    llvm::MachineInstrBuilder MIB)

Description

Insert an existing instruction at the insertion point.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:343

Parameters

llvm::MachineInstrBuilder MIB

¶Optional<llvm::MachineInstrBuilder>
materializePtrAdd(llvm::Register& Res,
                  llvm::Register Op0,
                  const llvm::LLT& ValueTy,
                  uint64_t Value)

Description

Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value) G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0, storing the resulting pointer in \p Res. If \p Value is zero then no G_PTR_ADD or G_CONSTANT will be created and

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:438

Parameters

llvm::Register& Res
llvm::Register Op0
const llvm::LLT& ValueTy
uint64_t Value

Returns

a MachineInstrBuilder for the newly created instruction.

¶void recordInsertion(llvm::MachineInstr* MI) const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:233

Parameters

llvm::MachineInstr* MI

¶void setCSEInfo(llvm::GISelCSEInfo* Info)

Description

@ }

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:300

Parameters

llvm::GISelCSEInfo* Info

¶void setChangeObserver(
    llvm::GISelChangeObserver& Observer)

Description

@ }

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:316

Parameters

llvm::GISelChangeObserver& Observer

¶void setDebugLoc(const llvm::DebugLoc& DL)

Description

Set the debug location to \p DL for all the next build instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:321

Parameters

const llvm::DebugLoc& DL

¶void setInsertPt(llvm::MachineBasicBlock& MBB,
                 MachineBasicBlock::iterator II)

Description

Set the insertion point before the specified position.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:297

Parameters

llvm::MachineBasicBlock& MBB
MachineBasicBlock::iterator II

¶void setInstr(llvm::MachineInstr& MI)

Description

Set the insertion point to before MI.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:313

Parameters

llvm::MachineInstr& MI

¶void setMBB(llvm::MachineBasicBlock& MBB)

Description

Set the insertion point to the end of \p MBB.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:309

Parameters

llvm::MachineBasicBlock& MBB

¶void setMF(llvm::MachineFunction& MF)

Description

@ { Set the MachineFunction where to build instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:305

Parameters

llvm::MachineFunction& MF

¶void stopObservingChanges()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:317

¶void validateBinaryOp(const llvm::LLT& Res,
                      const llvm::LLT& Op0,
                      const llvm::LLT& Op1)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:228

Parameters

const llvm::LLT& Res
const llvm::LLT& Op0
const llvm::LLT& Op1

¶void validateSelectOp(const llvm::LLT& ResTy,
                      const llvm::LLT& TstTy,
                      const llvm::LLT& Op0Ty,
                      const llvm::LLT& Op1Ty)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:231

Parameters

const llvm::LLT& ResTy
const llvm::LLT& TstTy
const llvm::LLT& Op0Ty
const llvm::LLT& Op1Ty

¶void validateShiftOp(const llvm::LLT& Res,
                     const llvm::LLT& Op0,
                     const llvm::LLT& Op1)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:229

Parameters

const llvm::LLT& Res
const llvm::LLT& Op0
const llvm::LLT& Op1

¶void validateTruncExt(const llvm::LLT& Dst,
                      const llvm::LLT& Src,
                      bool IsExtend)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:226

Parameters

const llvm::LLT& Dst
const llvm::LLT& Src
bool IsExtend

¶virtual ~MachineIRBuilder()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:243

class MachineIRBuilder

Declaration

Description

Method Overview

Methods

¶MachineIRBuilder()

Description

¶MachineIRBuilder(llvm::MachineFunction& MF)

Parameters

¶MachineIRBuilder(llvm::MachineInstr& MI)

Parameters

¶MachineIRBuilder( const llvm::MachineIRBuilderState& BState)

Parameters

¶llvm::MachineInstrBuilder buildAShr( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)

Parameters

¶llvm::MachineInstrBuilder buildAdd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAddrSpaceCast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)

Description

Parameters

¶llvm::MachineInstrBuilder buildAnd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAnyExt( const llvm::DstOp& Res, const llvm::SrcOp& Op)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAnyExtOrTrunc( const llvm::DstOp& Res, const llvm::SrcOp& Op)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicCmpXchg( llvm::Register OldValRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicCmpXchgWithSuccess( llvm::Register OldValRes, llvm::Register SuccessRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMW( unsigned int Opcode, const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWAdd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWAnd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWFAdd( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)

Description

Parameters

¶llvm::MachineInstrBuilder buildAtomicRMWFSub( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)

Description

Parameters

¶llvm::MachineInstrBuilder buildAtomicRMWMax( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWMin( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWNand( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWOr( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWSub( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶`MachineIRBuilder()`

¶`MachineIRBuilder(llvm::MachineFunction& MF)`

¶`MachineIRBuilder(llvm::MachineInstr& MI)`

¶`MachineIRBuilder( const llvm::MachineIRBuilderState& BState)`

¶`llvm::MachineInstrBuilder buildAShr( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)`

¶`llvm::MachineInstrBuilder buildAdd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)`

¶`llvm::MachineInstrBuilder buildAddrSpaceCast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildAnd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1)`

¶`llvm::MachineInstrBuilder buildAnyExt( const llvm::DstOp& Res, const llvm::SrcOp& Op)`

¶`llvm::MachineInstrBuilder buildAnyExtOrTrunc( const llvm::DstOp& Res, const llvm::SrcOp& Op)`

¶`llvm::MachineInstrBuilder buildAtomicCmpXchg( llvm::Register OldValRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicCmpXchgWithSuccess( llvm::Register OldValRes, llvm::Register SuccessRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMW( unsigned int Opcode, const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWAdd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWAnd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWFAdd( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWFSub( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWMax( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWMin( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWNand( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWOr( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWSub( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWUmax( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWUmin( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWXchg( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWXor( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildBitcast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildBlockAddress( llvm::Register Res, const llvm::BlockAddress* BA)`

¶`llvm::MachineInstrBuilder buildBoolExt( const llvm::DstOp& Res, const llvm::SrcOp& Op, bool IsFP)`

¶`llvm::MachineInstrBuilder buildBr( llvm::MachineBasicBlock& Dest)`

¶`llvm::MachineInstrBuilder buildBrCond( llvm::Register Tst, llvm::MachineBasicBlock& Dest)`

¶`llvm::MachineInstrBuilder buildBrIndirect( llvm::Register Tgt)`

¶`llvm::MachineInstrBuilder buildBrJT( llvm::Register TablePtr, unsigned int JTI, llvm::Register IndexReg)`

¶`llvm::MachineInstrBuilder buildBuildVector( const llvm::DstOp& Res, ArrayRef<llvm::Register> Ops)`

¶`llvm::MachineInstrBuilder buildBuildVectorTrunc( const llvm::DstOp& Res, ArrayRef<llvm::Register> Ops)`

¶`llvm::MachineInstrBuilder buildCTLZ( const llvm::DstOp& Dst, const llvm::SrcOp& Src0)`

¶`llvm::MachineInstrBuilder buildCTLZ_ZERO_UNDEF( const llvm::DstOp& Dst, const llvm::SrcOp& Src0)`

¶`llvm::MachineInstrBuilder buildCTPOP( const llvm::DstOp& Dst, const llvm::SrcOp& Src0)`

¶`llvm::MachineInstrBuilder buildCTTZ( const llvm::DstOp& Dst, const llvm::SrcOp& Src0)`

¶`llvm::MachineInstrBuilder buildCTTZ_ZERO_UNDEF( const llvm::DstOp& Dst, const llvm::SrcOp& Src0)`

¶`llvm::MachineInstrBuilder buildCast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildConcatVectors( const llvm::DstOp& Res, ArrayRef<llvm::Register> Ops)`