class MicroOpQueueStage

Declaration

class MicroOpQueueStage : public Stage { /* full declaration omitted */ };

Description

A stage that simulates a queue of instruction opcodes.

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:26

Inherits from: Stage

Method Overview

Inherited from Stage:

Methods

MicroOpQueueStage(unsigned int Size,
                  unsigned int IPC = 0,
                  bool ZeroLatencyStage = true)

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:64

Parameters

unsigned int Size
unsigned int IPC = 0
bool ZeroLatencyStage = true

llvm::Error cycleEnd()

Description

Called once at the end of each cycle.

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:82

llvm::Error cycleStart()

Description

Called once at the start of each cycle. This can be used as a setup phase to prepare for the executions during the cycle.

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:81

llvm::Error execute(llvm::mca::InstRef& IR)

Description

The primary action that this stage performs on instruction IR.

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:80

Parameters

llvm::mca::InstRef& IR

bool hasWorkToComplete() const

Description

Returns true if some instructions are still executing this stage.

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:76

bool isAvailable(
    const llvm::mca::InstRef& IR) const

Description

Returns true if it can execute IR during this cycle.

Declared at: llvm/include/llvm/MCA/Stages/MicroOpQueueStage.h:67

Parameters

const llvm::mca::InstRef& IR