class MCInstrAnalysis

Declaration

class MCInstrAnalysis { /* full declaration omitted */ };

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:27

Member Variables

protected const llvm::MCInstrInfo* Info

Method Overview

• public MCInstrAnalysis(const llvm::MCInstrInfo * Info)
• public virtual bool clearsSuperRegisters(const llvm::MCRegisterInfo & MRI, const llvm::MCInst & Inst, llvm::APInt & Writes) const
• public virtual bool evaluateBranch(const llvm::MCInst & Inst, uint64_t Addr, uint64_t Size, uint64_t & Target) const
• public virtual Optional<uint64_t> evaluateMemoryOperandAddress(const llvm::MCInst & Inst, uint64_t Addr, uint64_t Size) const
• public virtual std::vector<std::pair<uint64_t, uint64_t>> findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, uint64_t GotPltSectionVA, const llvm::Triple & TargetTriple) const
• public virtual bool isBranch(const llvm::MCInst & Inst) const
• public virtual bool isCall(const llvm::MCInst & Inst) const
• public virtual bool isConditionalBranch(const llvm::MCInst & Inst) const
• public virtual bool isDependencyBreaking(const llvm::MCInst & MI, llvm::APInt & Mask, unsigned int CPUID) const
• public virtual bool isIndirectBranch(const llvm::MCInst & Inst) const
• public virtual bool isOptimizableRegisterMove(const llvm::MCInst & MI, unsigned int CPUID) const
• public virtual bool isReturn(const llvm::MCInst & Inst) const
• public virtual bool isTerminator(const llvm::MCInst & Inst) const
• public virtual bool isUnconditionalBranch(const llvm::MCInst & Inst) const
• public virtual bool isZeroIdiom(const llvm::MCInst & MI, llvm::APInt & Mask, unsigned int CPUID) const
• public virtual ~MCInstrAnalysis()

Methods

¶MCInstrAnalysis(const llvm::MCInstrInfo* Info)

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:34

Parameters

const llvm::MCInstrInfo* Info

¶virtual bool clearsSuperRegisters(
    const llvm::MCRegisterInfo& MRI,
    const llvm::MCInst& Inst,
    llvm::APInt& Writes) const

Description

Returns true if at least one of the register writes performed by Example: on X86-64, a write to EAX implicitly clears the upper half of RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit instruction implicitly clears the upper portion of the correspondent YMM register. This method also updates an APInt which is used as mask of register writes. There is one bit for every explicit/implicit write performed by the instruction. If a write implicitly clears its super-registers, then the corresponding bit is set (vic. the corresponding bit is cleared). The first bits in the APint are related to explicit writes. The remaining bits are related to implicit writes. The sequence of writes follows the machine operand sequence. For implicit writes, the sequence is defined by the MCInstrDesc. The assumption is that the bit-width of the APInt is correctly set by the caller. The default implementation conservatively assumes that none of the writes clears the upper portion of a super-register.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:86

Parameters

const llvm::MCRegisterInfo& MRI

const llvm::MCInst& Inst

implicitly clears the upper portion of all super-registers.

llvm::APInt& Writes

¶virtual bool evaluateBranch(
    const llvm::MCInst& Inst,
    uint64_t Addr,
    uint64_t Size,
    uint64_t& Target) const

Description

Given a branch instruction try to get the address the branch targets. Return true on success, and the address in Target.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:152

Parameters

const llvm::MCInst& Inst

uint64_t Addr

uint64_t Size

uint64_t& Target

¶virtual Optional<uint64_t>
evaluateMemoryOperandAddress(
    const llvm::MCInst& Inst,
    uint64_t Addr,
    uint64_t Size) const

Description

Given an instruction tries to get the address of a memory operand. Returns the address on success.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:157

Parameters

const llvm::MCInst& Inst

uint64_t Addr

uint64_t Size

¶virtual std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(
    uint64_t PltSectionVA,
    ArrayRef<uint8_t> PltContents,
    uint64_t GotPltSectionVA,
    const llvm::Triple& TargetTriple) const

Description

Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:163

Parameters

uint64_t PltSectionVA

ArrayRef<uint8_t> PltContents

uint64_t GotPltSectionVA

const llvm::Triple& TargetTriple

¶virtual bool isBranch(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:37

Parameters

const llvm::MCInst& Inst

¶virtual bool isCall(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:53

Parameters

const llvm::MCInst& Inst

¶virtual bool isConditionalBranch(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:41

Parameters

const llvm::MCInst& Inst

¶virtual bool isDependencyBreaking(
    const llvm::MCInst& MI,
    llvm::APInt& Mask,
    unsigned int CPUID) const

Description

Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID . The value computed by a dependency breaking instruction is not dependent on the inputs. An example of dependency breaking instruction on X86 is `XOR %eax, %eax`. If MI is a dependency breaking instruction for subtarget CPUID, then Mask can be inspected to identify independent operands. Essentially, each bit of the mask corresponds to an input operand. Explicit operands are laid out first in the mask; implicit operands follow explicit operands. Bits are set for operands that are independent. Note that the number of bits in Mask may not be equivalent to the sum of explicit and implicit operands in MI. Operands that don't have a corresponding bit in Mask are assumed "not independente". The only exception is for when Mask is all zeroes. That means: explicit input operands of MI are independent.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:133

Parameters

const llvm::MCInst& MI

llvm::APInt& Mask

unsigned int CPUID

¶virtual bool isIndirectBranch(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:49

Parameters

const llvm::MCInst& Inst

¶virtual bool isOptimizableRegisterMove(
    const llvm::MCInst& MI,
    unsigned int CPUID) const

Description

Returns true if MI is a candidate for move elimination. Different subtargets may apply different constraints to optimizable register moves. For example, on most X86 subtargets, a candidate for move elimination cannot specify the same register for both source and destination.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:144

Parameters

const llvm::MCInst& MI

unsigned int CPUID

¶virtual bool isReturn(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:57

Parameters

const llvm::MCInst& Inst

¶virtual bool isTerminator(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:61

Parameters

const llvm::MCInst& Inst

¶virtual bool isUnconditionalBranch(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:45

Parameters

const llvm::MCInst& Inst

¶virtual bool isZeroIdiom(const llvm::MCInst& MI,
                         llvm::APInt& Mask,
                         unsigned int CPUID) const

Description

Returns true if MI is a dependency breaking zero-idiom for the given subtarget. Mask is used to identify input operands that have their dependency broken. Each bit of the mask is associated with a specific input operand. Bits associated with explicit input operands are laid out first in the mask; implicit operands come after explicit operands. Dependencies are broken only for operands that have their corresponding bit set. Operands that have their bit cleared, or that don't have a corresponding bit in the mask don't have their dependency broken. Note that Mask may not be big enough to describe all operands. The assumption for operands that don't have a correspondent bit in the mask is that those are still data dependent. The only exception to the rule is for when Mask has all zeroes. A zero mask means: dependencies are broken for all explicit register operands.

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:108

Parameters

const llvm::MCInst& MI

llvm::APInt& Mask

unsigned int CPUID

¶virtual ~MCInstrAnalysis()

Declared at: llvm/include/llvm/MC/MCInstrAnalysis.h:35