class TargetPassConfig

Declaration

class TargetPassConfig : public ImmutablePass { /* full declaration omitted */ };

Description

Target-Independent Code Generator Pass Configuration Options. This is an ImmutablePass solely for the purpose of exposing CodeGen options to the internals of other CodeGen passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:83

Inherits from: ImmutablePass

Member Variables

protected llvm::LLVMTargetMachine* TM
protected llvm::PassConfigImpl* Impl = nullptr
protected bool Initialized = false
protected bool DisableVerify = false
protected bool EnableTailMerge = true
Default setting for -enable-tail-merge on this target.
protected bool RequireCodeGenSCCOrder = false
Require processing of functions such that callees are generated before callers.
public static char ID

Method Overview

Inherited from ImmutablePass:

Inherited from ModulePass:

Inherited from Pass:

Methods

TargetPassConfig(
    llvm::LLVMTargetMachine& TM,
    llvm::legacy::PassManagerBase& pm)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:140

Parameters

llvm::LLVMTargetMachine& TM
llvm::legacy::PassManagerBase& pm

TargetPassConfig()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:142

virtual void addBlockPlacement()

Description

Add standard basic block placement passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:410

virtual void addCodeGenPrepare()

Description

Add pass to prepare the LLVM IR for code generation. This should be done before exception handling preparation passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:230

bool addCoreISelPasses()

Description

Add the actual instruction selection passes. This does not include preparation passes on IR.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:137

virtual void addFastRegAlloc()

Description

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:367

virtual bool addGCPasses()

Description

addGCPasses - Add late codegen passes that analyze code for garbage collection. This should return true if GC info should be printed after these passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:407

virtual bool addGlobalInstructionSelect()

Description

This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:271

virtual bool addILPOpts()

Description

Add passes that optimize instruction level parallelism for out-of-order targets. These passes are run while the machine code is still in SSA form, so they can use MachineTraceMetrics to control their heuristics. All passes added here should preserve the MachineDominatorTree, MachineLoopInfo, and MachineTraceMetrics analyses.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:353

virtual void addIRPasses()

Description

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:223

virtual bool addIRTranslator()

Description

This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:244

bool addISelPasses()

Description

High level function that adds all passes necessary to go from llvm IR representation to the MI representation. Adds IR based lowering and target specific optimization passes and finally the core instruction selection passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:219

Returns

true if an error occurred, false otherwise.

virtual void addISelPrepare()

Description

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:234

virtual bool addInstSelector()

Description

addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:238

virtual bool addLegalizeMachineIR()

Description

This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:252

virtual void addMachineLateOptimization()

Description

Add passes that optimize machine instructions after register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:398

virtual void addMachinePasses()

Description

Add the complete, standard set of LLVM CodeGen passes. Fully developed targets will not generally override this.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:275

virtual void addMachineSSAOptimization()

Description

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:345

virtual void addOptimizedRegAlloc()

Description

addOptimizedRegAlloc - Add passes related to register allocation. LLVMTargetMachine provides standard regalloc passes for most targets.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:371

llvm::AnalysisID addPass(llvm::AnalysisID PassID,
                         bool verifyAfter = true,
                         bool printAfter = true)

Description

Add a CodeGen pass at this point in the pipeline after checking overrides. Return the pass that was added, or zero if no pass was added.@p printAfter if true and adding a machine function pass add an extra machine printer pass afterwards@p verifyAfter if true and adding a machine function pass add an extra machine verification pass afterwards.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:432

Parameters

llvm::AnalysisID PassID
bool verifyAfter = true
bool printAfter = true

void addPass(llvm::Pass* P,
             bool verifyAfter = true,
             bool printAfter = true)

Description

Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options. Takes ownership of the pass.@p printAfter if true and adding a machine function pass add an extra machine printer pass afterwards@p verifyAfter if true and adding a machine function pass add an extra machine verification pass afterwards.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:442

Parameters

llvm::Pass* P
bool verifyAfter = true
bool printAfter = true

void addPassesToHandleExceptions()

Description

Add passes to lower exception handling for the code generator.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:226

virtual void addPostRegAlloc()

Description

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:395

virtual void addPostRewrite()

Description

Add passes to be run immediately after virtual registers are rewritten to physical registers.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:391

virtual void addPreEmitPass()

Description

This pass may be implemented by targets that want to run passes immediately before machine code is emitted.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:414

virtual void addPreEmitPass2()

Description

Targets may add passes immediately before machine code is emitted in this callback. This is called even later than `addPreEmitPass`.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:421

virtual void addPreGlobalInstructionSelect()

Description

This method may be implemented by targets that want to run passes immediately before the (global) instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:265

virtual bool addPreISel()

Description

addPreISelPasses - This method should add any "last minute" LLVM->LLVM passes (which are run just before instruction selector).

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:339

virtual void addPreLegalizeMachineIR()

Description

This method may be implemented by targets that want to run passes immediately before legalization.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:248

virtual void addPreRegAlloc()

Description

This method may be implemented by targets that want to run passes immediately before register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:359

virtual void addPreRegBankSelect()

Description

This method may be implemented by targets that want to run passes immediately before the register bank selection.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:256

virtual bool addPreRewrite()

Description

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers. These passes must preserve VirtRegMap and LiveIntervals, and when running after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. When these passes run, VirtRegMap contains legal physreg assignments for all virtual registers. Note if the target overloads addRegAssignAndRewriteOptimized, this may not be honored. This is also not generally used for the the fast variant, where the allocation and rewriting are done in one pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:385

virtual void addPreSched2()

Description

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:402

void addPrintPass(const std::string& Banner)

Description

Add a pass to print the machine function if printing is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:303

Parameters

const std::string& Banner

virtual bool addRegAssignmentFast()

Description

Add core register alloator passes which do the actual register assignment and rewriting.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:450

Returns

true if any passes were added.

virtual bool addRegAssignmentOptimized()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:451

virtual bool addRegBankSelect()

Description

This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:261

void addVerifyPass(const std::string& Banner)

Description

Add a pass to perform basic verification of the machine function if verification is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:307

Parameters

const std::string& Banner

virtual llvm::ScheduleDAGInstrs*
createMachineScheduler(
    llvm::MachineSchedContext* C) const

Description

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level. This can also be used to plug a new MachineSchedStrategy into an instance of the standard ScheduleDAGMI: return new ScheduleDAGMI(C, std::make_unique <MyStrategy >(C), /*RemoveKillFlags=*/false) Return NULL to select the default (generic) machine scheduler.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:287

Parameters

llvm::MachineSchedContext* C

virtual llvm::ScheduleDAGInstrs*
createPostMachineScheduler(
    llvm::MachineSchedContext* C) const

Description

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:294

Parameters

llvm::MachineSchedContext* C

virtual llvm::FunctionPass* createRegAllocPass(
    bool Optimized)

Description

addMachinePasses helper to create the target-selected or overriden regalloc pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:446

Parameters

bool Optimized

virtual llvm::FunctionPass*
createTargetRegisterAllocator(bool Optimized)

Description

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:363

Parameters

bool Optimized

void disablePass(llvm::AnalysisID PassID)

Description

Allow the target to disable a specific standard pass by default.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:195

Parameters

llvm::AnalysisID PassID

void enablePass(llvm::AnalysisID PassID)

Description

Allow the target to enable a specific standard pass by default.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:192

Parameters

llvm::AnalysisID PassID

int getCSEConfig() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:324

bool getEnableTailMerge() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:174

std::string getLimitedCodeGenPipelineReason(
    const char* Separator = "/") const

Description

If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options, separated by \p Separator that caused this pipeline to be limited.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:170

Parameters

const char* Separator = "/"

CodeGenOpt::Level getOptLevel() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:156

bool getOptimizeRegAlloc() const

Description

Return true if the optimized regalloc pipeline is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:208

llvm::IdentifyingPassPtr getPassSubstitution(
    llvm::AnalysisID StandardID) const

Description

Return the pass substituted for StandardID by the target. If no substitution exists, return StandardID.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:201

Parameters

llvm::AnalysisID StandardID

template <typename TMC>
TMC& getTM() const

Description

Get the right type of TargetMachine for this target.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:149

Templates

TMC

static bool hasLimitedCodeGenPipeline()

Description

Returns true if one of the `-start-after`, `-start-before`, `-stop-after` or `-stop-before` options is set.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:160

void insertPass(
    llvm::AnalysisID TargetPassID,
    llvm::IdentifyingPassPtr InsertedPassID,
    bool VerifyAfter = true,
    bool PrintAfter = true)

Description

Insert InsertedPassID pass after TargetPassID pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:188

Parameters

llvm::AnalysisID TargetPassID
llvm::IdentifyingPassPtr InsertedPassID
bool VerifyAfter = true
bool PrintAfter = true

virtual bool isGISelCSEEnabled() const

Description

Check whether continuous CSE should be enabled in GISel passes. By default, it's enabled for non O0 levels.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:321

bool isGlobalISelAbortEnabled() const

Description

Check whether or not GlobalISel should abort on error. When this is disabled, GlobalISel will fall back on SDISel instead of erroring out.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:312

bool isPassSubstitutedOrOverridden(
    llvm::AnalysisID ID) const

Description

Return true if the pass has been substituted by the target or overridden on the command line.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:205

Parameters

llvm::AnalysisID ID

void printAndVerify(const std::string& Banner)

Description

printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:300

Parameters

const std::string& Banner

virtual bool
reportDiagnosticWhenGlobalISelFallback() const

Description

Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path. In other words, it will emit a diagnostic when GlobalISel failed and isGlobalISelAbortEnabled is false.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:317

bool requiresCodeGenSCCOrder() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:177

void setDisableVerify(bool Disable)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:172

Parameters

bool Disable

void setEnableTailMerge(bool Enable)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:175

Parameters

bool Enable

void setInitialized()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:154

void setOpt(bool& Opt, bool Val)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:328

Parameters

bool& Opt
bool Val

void setRequiresCodeGenSCCOrder(
    bool Enable = true)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:178

Parameters

bool Enable = true

void substitutePass(
    llvm::AnalysisID StandardID,
    llvm::IdentifyingPassPtr TargetID)

Description

Allow the target to override a specific pass without overriding the pass pipeline. When passes are added to the standard pipeline at the point where StandardID is expected, add TargetID in its place.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:185

Parameters

llvm::AnalysisID StandardID
llvm::IdentifyingPassPtr TargetID

bool usingDefaultRegAlloc() const

Description

Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:212

static bool willCompleteCodeGenPipeline()

Description

Returns true if none of the `-stop-before` and `-stop-after` options is set.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:164

~TargetPassConfig()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:144